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  1. Hi, From the UVM class reference manual, copy is deep copy, and clone is exact copy, so what does 'exact' copy mean? I guess clone is also deep copy, but the difference with copy(), is that clone() is virtual method, but copy() is not, need your confirm, thanks. BR MEIXIAO
  2. Hi, When I try to use a parametered based callback class, IUS tool will report the following warning, seems it is the type mismatched, but I am confused that the callback task can still work, so does anyone tell me how to remove such warning? UVM_WARNING @ 0.00 ns: reporter [CBUNREG] Callback tb_axi_mst_drv_cb cannot be registered with object uvm_test_top.tb_axi_ovc_self_loop_inst.axi_ovc_mst.master.driver because callback type uvm_callback is not registered with object type uvm_driver #(REQ,RSP) I defined my callback class as follows: typedef class axi_master_driver; typedef class axi_master_driver_cb; typedef uvm_callbacks #(axi_master_driver, axi_master_driver_cb) axi_master_driver_cbs_t; virtual class axi_master_driver_cb #(axi_if_pkg::tIfParams IF_PARAMS = axi_if_pkg::AXI_DEFAULT) extends uvm_callback; virtual task pre_process_trans(axi_master_driver #(IF_PARAMS) driver, ref axi_trans_item #(IF_PARAMS) tr); endtask function new(string name="axi_mst_drv_cb_inst");// will include scoreboard handler later?? super.new(name); endfunction endclass: axi_master_driver_cb And declare my driver as follows: class axi_master_driver #(axi_if_pkg::tIfParams IF_PARAMS = axi_if_pkg::AXI_DEFAULT) extends uvm_driver; `uvm_component_param_utils(axi_master_driver #(IF_PARAMS)) ...... `uvm_register_cb(axi_master_driver #(IF_PARAMS), axi_master_driver_cb) ...... endclass: axi_master_driver BR MEIXIAO
  3. I am not quite understand item 2, I know the method about how to pass down the parameter to class components like driver/monitor/agents, but how to pass down the parameter for interface? Seems we can not use uvm_config_db::set to pass parameter to interface, is that right?
  4. But the fact is that, I want to implement a fully parametered UVC, means that the UVC interface 'DATAMSB' can be changed according to the TB requirements, so I can not perdict DATAMSB value in my UVC env, the only way is to set a default value 32 to it, and change it to 64 in module top, is there some way to implement this in UVM1.0p1?
  5. Hi, Today, I met a new issue with UVM1.0p1, I want to set a paramter based interface from module top level to my env, but it is unsuccessful, I don't why, please help to see if I made mistakes, thanks, here are what I have done: 1. create the parameter interface like this: interface ubus_if_parameter (parameter int DATAMSB=32) ; ... endinterface:ubus_if_parameter 2. in my env, declare such interface like this: virtual interface ubus_if_parameter vif_para;//leave the DATAMSB as default value 32 3. in module top level: declare such interface as: ubus_if_parameter #(.DATAMSB(64)) vif_para();//change the DATAMSB value as 64 But the problem is that, if set as the following line: uvm_config_db#(virtual ubus_if_parameter)::set(uvm_root::get(), "*", "vif_para", vif_para); then, IUS will report : ncelab: *E,TYCMPAT (./ubus_tb_top.sv,58|92): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface ubus_if_parameter#(.DATAMSB(32))' but found an incompatible 'ubus_if_parameter#(.DATAMSB(62)) instance' instead). But if I set as: uvm_config_db#(virtual ubus_if_parameter#(.DATAMSB(62)))::set(uvm_root::get(), "*", "vif_para", vif_para); I found that the vif_para in my env is null pointer. So I want to ask where is wrong with my method, how to use uvm_config_db to set parameter based interface to my env?Thanks a lot! BR MEIXIAO
  6. Hi, Recently, I have a new question about UVM objections, firstly, I know that in ubus example, the base sequence will call 'raise_objection' in pre_body() and call 'low_objection' in post_body(), but the problem is that if I commented out these lines, meaning never use UVM objection in our TB, I found that the sequence will never start, the simulation will be quit at 0 time point. This is different from OVM2.1.1, so I want to ask why this simulation time is holding at 0ns? Is OBJECTION the mandatory feature for us? Thanks for your helps! BR MEIXIAO
  7. Does UVM_10X_DEV lib fix uvm_config_db wildcard setting bugs? http://www.uvmworld.org/forums/showthread.php?173-uvm_config_db-NOT-work-as-expected-UVM1.0p1
  8. do you mean UVM have released newer version of UVM1.0? I just checked with uvmworld website, it still uvm1.0p1, could you point us the weblink? Thanks
  9. As we know, the 'count' field in sequencer is removed from UVM1.0p1, so my 1st question is: how to stop the sequencer if we don't want it to start? my 2nd question is: if we never set the 'default_sequence' for one sequencer, then does this sequencer still work as it did in OVM? choose from the uvm_random_sequence or uvm_exhaustive_sequence or others? my 3rd question is: if we never use `uvm_declare_p_sequencer to declare p_sequencer, can we still call it and use it in our sequence? Thanks for your helps!
  10. why UVM removed `ovm_update_sequence_lib(_and_item) macros? Is there some other macro that can be used as the same function? Could you helps?
  11. I think it truly a potential bug in UVM1.0p1, so could you tell me how to work around this issue? It is so urgent to us as our TB uses a lot of wildcard settings.
  12. Hi, There are some parts of my codes, seems uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test*", 1) can not update test/test1/test2 values in TB_env, are there some thing wrong with my code? I just tried to use uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test1", 1), it works well, so I think my path is correct, could you help? Does UVM1.0 still support multi config or is that a potential bug in UVM1.0? 1. in TB env: class TB_env extends uvm_env; int test = 0; int test1 = 0; int test2 = 0; `uvm_component_utils_begin(tb_axi_ovc_self_loop) `uvm_field_int (test, UVM_ALL_ON) `uvm_field_int (test1, UVM_ALL_ON) `uvm_field_int (test2, UVM_ALL_ON) `uvm_component_utils_end virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction endclass 2. in Test case class testcase extends uvm_test; TB_env TB_env_inst; virtual function void build_phase(uvm_phase phase); super.build_phase(phase); uvm_config_db#(uvm_bitstream_t)::set(this, "TB_env_inst", "test*", 1); //create TB_env_inst endfunction endclass BR Mike
  13. I found that I can't mulit config inst as following in UVM1.0 In test case build_phase(), I tried to use uvm_config_db#(int)::set(this, "tb_env", "en_*", 1), but failed, could you helps? I original defined en_1, en_2, en_3 in tb_env, and register to the factory by `uvm_field_int(en_1, UVM_ALL_ON), `uvm_field_int(en_2, UVM_ALL_ON), `uvm_field_int(en_3, UVM_ALL_ON)
  14. Hi, as we know, in UVM1.0, the following line is replaced, original one: set_config_string("tb_axi_ovc_self_loop_inst.axi_ovc_mst.master.sequencer", "default_sequence", seq_name_s); replaced as: uvm_config_db#(uvm_object_wrapper)::set(this, "tb_axi_ovc_self_loop_inst.axi_ovc_mst.master.sequencer.run_phase", "default_sequence", axi_master_wr_rd_sequence::type_id::get()); But when I call uvm_top.print() in test case build_phase, I can not find the 'default_sequence' from that table, is there any way to tell me whether my sequence config is successful?Thanks! BR Mike
  15. Hi, I defined an integer in TB env(tb_env) called 'test', and in my sequence, I call assert(uvm_config_db#(int)::exists(uvm_top, "tb_env", "test", 1)); to check whether the sequence can obtain 'test' value, but assert failed. I just used `uvm_field_int(test, UVM_ALL_ON) to register to the factory. Could you help? Thanks a lot! BR Mike
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