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how to write more than one register using read and write functions

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I am using uvm standard register model , register adapter (bus2reg & reg2bus) to send and receive transaction to ral model and DUT.
and it is working fine if i do single read and write.(means i perform the 32 bit read n write using reg.read(status,address,data)reg.write(status,address,data))

My challange is that i have to perform the more than 32 bit transaction which performs the read and write on multiple registers,
If there any way to use the same reg.read/write method to perform more than one register

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You wont' be able to implement such a thing using a reg adapter. You're going to have to use the frontdoor mechanism. What I could imagine is that you could use some static member in the frontdoor to store multiple register items (that come from register reads and writes). Once you have enough to form a bigger burst, you could collect them into one big bus transfer and send them to the bus sequencer. Have a look in the UVM user guide for more details.

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I understand what you are saying .. but i have only one transaction of read and write and due to more payload bytes of transaction i need to perform read or write on multiple location , 
Actually my limitation is in adapter, adapter uvm_reg_bus_op class have only one data filed of register width so if i get more payload (>REG_DATA_WIDTH) in bus2reg or reg2bus for a single read and write transaction  ,i do not see the way to update the RAL Model automatically and performing the comparison.



I see that with creation of extension class  i can manage to send the reg2bus transaction with more than REG_WIDTH payload but i am not sure how can i manage bus2reg method to update the register model

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If you want to access only one register that is wider than the bus, then it's even easier. I'd for sure implement a custom frontdoor for that register. While trying to use the adapter you'll run into the limitation that the register map will chop the big access into pieces and you won't get a burst, but multiple individual transfers.

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