Jump to content

anming

Members
  • Content Count

    3
  • Joined

  • Last visited

About anming

  • Rank
    Member

Profile Information

  • Gender
    Male
  1. Thank you Bhunter1972 for response. I have created a stright forward testcase. By running it, you will see the build_phase does get called 4 times. I might miss something. `include "uvm_macros.svh" import uvm_pkg ::*; class test extends uvm_test; int count; `uvm_component_utils(test) function new ( string name ="test", uvm_component p = null); super.new(name, p); endfunction virtual function void build_phase(uvm_phase phase); `uvm_info(get_full_name(), "i am in build_phase", UVM_MEDIUM) endfunction virtual function void connect_phase(uvm_phase phase); `uvm_info(get_full_name(), "I am in connect_phase", UVM_MEDIUM) endfunction virtual task pre_reset_phase(uvm_phase phase); `uvm_info(get_full_name(), "i am in test pre_reset_phase", UVM_MEDIUM) endtask virtual task main_phase ( uvm_phase phase); phase.raise_objection(this); `uvm_info(get_full_name(), " i am in test main_phase ", UVM_MEDIUM) phase.drop_objection(this); endtask function void phase_ready_to_end(uvm_phase phase); super.phase_ready_to_end(phase); if ( phase.get_imp() == uvm_shutdown_phase::get() && count < 3) begin phase.jump(uvm_build_phase::get()); count++; end endfunction endclass module test; initial begin run_test("test"); end endmodule thanks andrwe
  2. Hi. in UVM, It is legal to have phase jump to any function phases. but it seems in below demonstration code it does not work as I expected. I expected the flag build_agt2 = 1 after the phase.jump(build_phase). class mycomponent extends uvm_component; ....... bit build_agt2; function void build_phase(uvm_phase phase); `create_agt1(); if ( build_agt2) `create_ag2() ; or // `override_agt1_by_agt2(); endfunction task run_phase; // change flag build_agt2 to 1; endtask function void phase_ready_to_end; // if the imp phase is in shutdown_phase // then phase.jump to build_phase endfunction
  3. do you think below works for you? my_seq extends uvm_seq; ..... rand int a; .... `uvm_do_with(tx, { tx.a = local:a, ......} ; endclass class my_complex_seq extends uvm_sequence... ...... my_seq seq; `uvm_do_with ( seq, { seq.a == 0 ......} ...... endclass
×
×
  • Create New...