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Hi all I'm trying to build a generlc verification environment for specific modules of mine, that essentially only differ (besides their actual implementation) by the number of inputs/outputs of a certain interface standard and the data_size of each of these interfaces. This leads to the point, that I like to have an environment, where I can set the number of interfaces and for each of these interfaces the data_size. Unfortunately this simple setup of non-dynamic pre-compile settings is getting me in a lot of trouble. (1) Sequence_Item class input_item #(int unsigned data_size) extends uvm_sequence_item; `uvm_object_param_utils(input_item) rand logic[data_size-1:0] data; ....... The first question that comes to mind writing this code is the following: Is it possible to factory overwrite a param. class with another specilisation of that same class (e.g. define a driver with input_item<32> and then factory overwrite it with input_item<42>)? Otherwise a item_base class would be necessary that than would be extended by this class. (2) Analysis Ports class env extends uvm_env; .... // need N = number of interfaces analysis ports between each monitor and scoreboard uvm_analysis_port #(input_item#(17)) ap_1; uvm_analysis_port #(input_item#(12)) ap_2; ..... uvm_analysis_port #(input_item#(42)) ap_N; .... Due to the different input_items all ports are of a different type. Therefore it is not possible to create an array of N=number_of_interfaces, which leads to this not being possible to implement. Furthermore the analysis_port/export classes cannot be overwritten through the means of the factory. (3) Virtual Sequence class top_vseq_base extends uvm_sequence #(uvm_sequence_item); `uvm_object_utils(top_vseq_base) uvm_sequencer #(input_item#(17)) seq_1; uvm_sequencer #(input_item#(12)) seq_2; ... uvm_sequencer #(input_item#(42)) seq_N; In the virtual sequence I essentially run into two problems: 1. The first one is the same problem as in (2) of not being able to create an array of different types or having a pre-processor for-loop 2. The other one is the fact, that I'm not able to get access to the number N . Even if they were all of the same type and I would declare a dynamic array, there is no build_phase and no way to get informations through either the config_db or "p_sequencer.variable". I could put a member variable into the virtual sequencer, but I'm not sure if it is a good idea/possible to create a dynamic array in the body method. General Solutions so far: I only see two solutions here ... 1. Defining a gigantic input_item with data_size of 256/512 and then cut it everywhere. But unfortunately I will be in need of an array of completely different items in the next version of this environment anyhow. The reason for that is, that I would like to group a bunch of M different interfaces into one environment, all of them running a different item. Therefore the analysis_ports would all run a different item. 2. Just building a code generator, in which the user sets all parameters, creating the necessary environment for the given DUT. If you have any input, I would be glad to hear it. Thanks Marcel