Jump to content

kiranbhaskar

Members
  • Posts

    22
  • Joined

  • Last visited

kiranbhaskar's Achievements

Member

Member (1/2)

1

Reputation

  1. Hi Janick, I was able to solve this problem ..By doing the following things in the stimulus path (driver), I wrote the read back value from the VIF to the transaction that i was driving .. ie trans.data = vif.data; And the now the messages look like this [Reg_predict] observed UVM_WRITE transaction to the regmodel.spi_rf.register: value = `h42 (message is printed from uvm_reg_sequence.svh -- line no 710 ) [Regmodel] wrote register via map regmodel.spi_rf.register = `h42 (message is printed from uvm_reg.svh -- line no 2299) [Reg_predict] observed UVM_READ transaction to the regmodel.spi_rf.register: value = `h42 (message is printed from uvm_reg_sequence.svh -- line no 710 ) [Regmodel] read register via map regmodel.spi_rf.register = `h42 (message is printed from uvm_reg.svh -- line no 2299) From what i understand [Regmodel] message is controlled from the stimulus side and [Regpredict] message is controlled from the monitor side. The model is only updated when the [Regpredict] happens. Is my understanding correct? And when i use a mirror method the value in the [regmodel] message (ie stimulus) is checked against the mirrored value in the register model and not the value in the [Regpredict] message.Any particular reason? Regards, Kiran Bhaskar
  2. Hi Janick, If the predictor is doing the update on the register model ,why does the write and read to the register model happen twice. as shown in the messages below. [Reg_predict] observed UVM_WRITE transaction to the regmodel.spi_rf.register: value = `h42 (message is printed from uvm_reg_sequence.svh -- line no 710 ) [Regmodel] wrote register via map regmodel.spi_rf.register = `h42 (message is printed from uvm_reg.svh -- line no 2299) [Reg_predict] observed UVM_READ transaction to the regmodel.spi_rf.register: value = `h42 (message is printed from uvm_reg_sequence.svh -- line no 710 ) [Regmodel] read register via map regmodel.spi_rf.register = `h0 (message is printed from uvm_reg.svh -- line no 2299) can you please clarify what is the difference in the two messages and when is the actual update happening .(FYI -- the two updates are not in sync ie [Reg_predict] happens first and then [regmodel]) Regards, Kiran Bhaskar
  3. Hi , I have a small question regarding the register model updation, when i am using the explicit monitoring does the predictor update the register model or the driver ? i see these two messages what is the difference b/w the two and which is doing the update on the model. [Regmodel] wrote register via map regmodel.spi_rf.register = `h42 ( i see that this is controlled by the driver) [Reg_predict] observed UVM_WRITE transaction to the regmodel.spi_rf.register: value = `h42 (This is controlled by the monitor) Regards, Kiran Bhaskar
  4. I do the following in my register sequence write_reg(regmodel.reg_file.Reg_A,status,data1) i see the data written to the DUT Then i check the desired value using desired_value = regmodel.reg_file.Reg_A.get(); I see the desired value is same as the data1 But when i do a Read_reg(regmodel.reg_file.Reg_A,status,expected_value) The expected value is always zero. I have tried everything and not able to figure out why this is happening. Regards, Kiran Bhaskar
  5. Hi everyone, I read a register using the register model using explicit monitoring. I see that the REG_PREDICT does a correct read on the register with the correct value. But the value read via map is always zero. Wat can be the reason? Regards, kiran Bhaskar
  6. I am using a pipelined bus as shown below 1 -- 2 -- 3 -- 4 addr1--data1,addr2--data2,addr3--data3,addr4 I am using explicit monitoring for my prediction But when i am using the mirror function to check for readback value i am getting an error as the mirrror value first does a check on the readback value and then does the updation. ie when i use a mirror for addr2 register, the error is thrown up in cycle 2 when the actual update happens in cycle 3. How do i go around this problem.I am also not able to use all the uvm_reg predefined sequences as all the predefined sequences use the mirror method for the comparision Regards, Kiran Bhaskar
  7. I did a small debug and i found that the problem is not with the read but it is with the mirror method. When you use the mirror method with the read and check mode( UVM_CHECK) The mirror method first does the check and then does the read.This throws me an error as the readback value is still not updated in the DUT. Is this a bug in the UVM. The mirror method should first read and then do the check as the read back value will be updated.
  8. I have a small problem with my register sequence and register predictor. I initiate the predefined test sequence provided by UVM for the reset check (uvm_reg_hw_reset_seq) I am using explicit monitoring to update the register model. I see that the the comparison b/w the DUT value and the register model value is happening at the start of the register access rather than the after the completion of the register access. I have set the auto prediction to 1 . Am i missing out on any configurations and is there a method to pull the register model to your waveform window to check the value reflecting the model Regards, kiran bhaskar
  9. i refered the "Step by step function verification with system verilog and ovm" by sasam iman This gives a nice start to understanding UVM and sytem verilog basics
  10. Hi, I have a register sequence which reads two registers and resets the register model and then updates the reset value to the DUT. my sequence is class xyz extends uvm_reg_sequence task body read_reg(regmodel.SPICR,status,data); read_reg(regmodel.SPISR,status,data); regmodel.reset(); update_reg(regmodel.SPIDR,status,data) //and all other registers in the model. end Problem: Simulation stops at regmodel.reset(). The same sequence if written in the following manner works fine. class xyz extends uvm_reg_sequence task body regmodel.reset(); read_reg(regmodel.SPICR,status,data); read_reg(regmodel.SPISR,status,data); update_reg(regmodel.SPIDR,status,data) //and all other registers in the model. end why does the simulation stop in the first sequence??? regards, KB
  11. Hi Uwes, Can i stop a seq when there are still items in the queue for instance , In my spi_seq i have body () { uvm_do_with(); //Can i stop the sequence here and continue my CPU seq uvm_do_with(); uvm_do_with(); } can i stop the sequence at the comment above and continue my CPU_seq My CPU_seq has body () { uvm_do_with(); //Can i stop the CPU sequence here and continue my SPI seq uvm_do_with(); uvm_do_with(); } can i stop the CPU sequence at the comment above and continue my SPI_seq
  12. Is there a mechanism for communicating between two sequences. I have a virtual sequence body task body() { uvm_do_on ( spi_seq, spi_sequencer) uvm_do_on ( cpu_seq, cpu_sequencer) } Is there a mechanism to stop SPI sequencer after one frame is sent and execute the CPU sequencer to read the register and then again continue SPI sequencer and then again read the register. Regards, Kiran Bhaskar
  13. Can i use grab , ungrab or lock and unlock in the body task of my sequence..if not how do i use it ? Wat is the diff b/w a grab and lock? wat is the significance of p_sequencer and m_sequencer?
  14. Try disabling the register in the build phase. Use REG:: instead of * in your set call.. uvm_resource_db#(bit)::set({"REG::", m_env.model.eq.MY_REGISTER.get_full_name(),".*"}, "NO_REG_BIT_BASH_TEST",1,this);
  15. Also add an uvm info in the body task and see if the message is printed. if the message is still not not printed check your configuration again. Also see your class hierarchy after running the simulator..and check if the sequencer driver and other things are created correctly. Regards, Kiran Bhaskar
×
×
  • Create New...