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UVM RAL - Register Verification for Different Access types

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I'm experimenting UVM RAL register verification for all the access types for registers and I'm experiencing the issue while using built-in sequence uvm_reg_access_seq. In my design I've implemented all the access types of register and while using mentioned sequence, RC and RS access types register are being written and then read which I believe should not happen by UVM reference guide. In UVM reference guide, by definition RO, RS and RC access types registers behavioral is mentioned below.


”RO” W: no effect, R: no effect

”RC” W: no effect, R: clears all bits

”RS” W: no effect, R: sets all bits


While RO registers being verified, following warning is given by UVM.

UVM_WARNING uvm_1.1d/reg/sequences/uvm_reg_access_seq.svh(107) @ 370: reporter@@reg_access_seq.single_reg_access_seq [uvm_reg_access_seq] Register 'model.mem_model.status_reg' has RO fields


But for RC and RS access types registers, I can see its trying to write via FRONTDOOR first and then reads BACKDOOR and finally there is data mismatch error is generated.



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