hevangel

Thanks for the explaination. I hope Accellera would clean it up in the IEEE-UVM standard to avoid having ambigious build order.

If you are using Cadence, try change "program test" to "module test" and see whether it solve your problem. I encountered SV threads scheduling issues when mixing class inside a program and sequence.get_next_item() in a module.

Hi, I notice something interesting in the build_phase order of uvm_component. The uvm_component at the same level are build in the alphabetatical order of the instance name. I expect the build order would be the same as the order I call the factory create function. I am wondering is the alphabetatical build order an intended feature of UVM or just some artifact of the implementation? I couldn't find any reference to this behavior in the UVM user guide or the class reference library. Thanks. Horace

To make uvm_random_stimulus useful, I think UVM should add a pull port to this class. The whole sequence/sequencer concept is based on pulls from the driver, uvm_random_stimulus does not fit well within this picture.