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OVM RGM Porting to UVM

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UVM_REG is a combination of VMM and OVM/UVM RGM.  It is the register open standard.  Tool generation is vendor specific (there are a lot of third party tools out there too -- which produce IP-XACT 1.5). For Cadence, iregGen takes in IP-XACT 1.5 xml.  This makes use of the vendor Extensions.  I think RAL has been expanded to produce the register model in SystemVerilog.

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depends what you means with RAL.


RAL (the register model) has been upgraded significantly and is now part of UVM. that register model is labeled UVMREG and the cadence register generator supports that model. that means ireggen can generate output for UVMREG. 


RAL (the register input description) is not supported by ireggen. ireggen main input is based upon the IPXACT standard.




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If you have a Register Model for UVM_REG and an adapter, you are good to go for upfront things like reading and writing registers using the UVM_REG API calls.


Now you have to decide on how to do prediction (this keeps the register model and the actual DUT synchronized.)

Initially you can go with auto-prediction (by default it is off), but eventually you will want to create a predictor for your bus transactions (which tracks both actual bus transactions coming from the register model and other sources.)


Turning on auto-predict will monitor your register transactions, but not all the transaction on the bus (outside of the register model.) This known as implicit prediction.


Explicit prediction is done when you extend uvm_reg_predictor:


Explicit Register Predictor The uvm_reg_predictor class defines a predictor component, which is used to update the register model’s mirror values based on transactions explicitly observed on a physical bus.


More on this in 5.9.3 on in the User's Guide



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