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Posted

Hi,

Your thread is not clear to me,But

According to my understanding about your post; You have put port in your component and trying to get from it in the same component;

For this; In your component class or in a higher class connect_phase do the following;

function void connect_phase(uvm_phase phase);

my_component.out.connect(my_fifo.blocking_put_export); //out is the put port

my_component.in.connect(my_fifo.blocking_get_export); // in is the get port

//////OR YOU CAN USE THIS WAY ALSO///

my_component.out.connect(in); //This is OK when there is no port interdependency between other components

endfunction

Hope this may help you. If not so, Just share in detail about your problem?

Thanks,

Regards,

Mahee.

Posted

Thanks for the reply Mahee,

I know the implementation of get_port & put_port.

What I wanted to know is the exact usage of the uvm component class "uvm_random_stimulus".

Is this same as atomic generator in VMM?

Thanks,

-Vinay

Posted

Hi kumarv. This is a great question. This class does indeed look very VMM-ish. I haven't used the class before, but I'd like to see if I could use it as my test case somehow (that seems to be the usage model), though test cases should be extended from uvm_test, not from uvm_random_stimulus. I'll play around with it.

  • 3 years later...
Posted

To make uvm_random_stimulus useful, I think UVM should add a pull port to this class.

The whole sequence/sequencer concept is based on pulls from the driver, uvm_random_stimulus does not fit well within this picture.

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