Problem about model in uvm_reg_sequence

[mrforever]

Hi all,

I met one problem about uvm_reg_sequence, the frame of my code likes as follows:

v_seq

      |--h_seq

             |--cfg_seq

                   |--bios_r_seq

 

v_sqr

     |--h_sqr

            |--cfg_sqr

 

env

     |--v_sqr

     |--reg_block_bios

 

test

     |--v_seq

 

Pieces of codes:

 

test.sv

foreach (v_seq.h_seq[i]) begin
  v_seq.h_seq[i].cfg_seq.bios_r_seq.model       = env.reg_block_bios[i];
end

 

v_seq.sv

  my_hsequence h_seq[];
  ...

  function new(string name = "my_vsequence");
    string inst_name;
    super.new(name);  
    h_seq = new[host_num];
    for (int i = 0; i < host_num; i++) begin
      inst_name = $sformatf("h_seq%0d", i);
      h_seq[i] = my_hsequence::type_id::create(inst_name,,get_full_name());
    end
  endfunction

 virtual task body();
    `uvm_info(get_type_name(),$sformatf("%0s starting...",
      get_sequence_path()), UVM_MEDIUM)

    foreach (h_seq[i]) begin
      fork
        `uvm_do_on(h_seq[i], p_sequencer.h_sqr[i])
      join
    end
  endtask : body
  ...
  `uvm_declare_p_sequencer(my_vsequencer)

h_seq.sv

config_sequence cfg_seq; 
... 
function new(string name = "my_hsequence");    
  super.new(name);    
  cfg_seq = config_sequence::type_id::create("cfg_seq",,get_full_name());    
  ...  
endfunction
...
virtual task body();    
  `uvm_info(get_type_name(),$sformatf("%0s starting...",      get_sequence_path()), UVM_MEDIUM)    
  // The first way    
  cfg_seq.start(p_sequencer.cfg_sqr, this);  
endtask 

 

bois_r_seq in cfg_seq.sv

 

  virtual task pre_body();
    //uvm_resource_db#(uvm_reg_block)::read_by_name("env", "reg_block_bios", model); 
    if (model == null) begin
      $display("model == null!!!");
    end
    $cast(reg_block_bios, model); 
    //if (!$cast(reg_block_bios, model)) begin
    //end   
  endtask : pre_body

 

v_sqr.sv

  my_hsequencer h_sqr[];
  ...
  function void build_phase(uvm_phase phase); 
    string inst_name;
    super.build_phase(phase);
    if(!uvm_config_db#(uvm_bitstream_t)::get(this, "", "host_num", host_num))
      `uvm_fatal("NOHOSTNUM",{"host number must be set for: ",get_full_name(),".host_num"});
    h_sqr = new[host_num];
    for (int i = 0; i < host_num; i++) begin
      inst_name = $sformatf("h_sqr%0d", i);
      h_sqr[i] = my_hsequencer::type_id::create(inst_name, this);
      uvm_config_db#(int)::set(this, inst_name, "ID", i);
    end
  endfunction : build_phase 

 

h_sqr.sv

  function void build_phase(uvm_phase phase);
    string cfg_inst;
    super.build_phase(phase);
    void'(uvm_config_db#(int)::get(this, "", "ID", ID));
    // instantiates sequencers and config_db
    cfg_inst = $sformatf("vcfg_sqr%0d", ID);
    cfg_sqr = my_config_sequencer::type_id::create(cfg_inst, this);
  endfunction : build_phase 

my_env.sv

function build_phase(uvm_phase phase)
    ...
    v_sqr = my_vsequencer::type_id::create("v_sqr", this);
    for (int i = 0; i < host_num; i++) begin
      $sformat(inst_name, "subenv[%0d]", i);
      subenv[i] = sub_env::type_id::create(inst_name, this);
      uvm_config_db#(int)::set(this, $sformatf("subenv[%0d]", i), "subenv_id", i);
    end
    ...
    reg_block_bios = new[host_num];
    for (int i = 0; i < host_num; i++) begin
      if(reg_block_bios[i] == null) begin
        inst_name = $sformatf("reg_block_bios%0d", i);
        reg_block_bios[i] = my_reg_block_bios::type_id::create(inst_name,,get_full_name());
        reg_block_bios[i].build();
        reg_block_bios[i].lock_model();
      end
    end
    ...
endfuction

  function void connect_phase(uvm_phase phase);
    string inst_name;
    super.connect_phase(phase);
    foreach(subenv[i]) begin 
      v_sqr.h_sqr[i].cfg_sqr = subenv[i].cfg_agt.cfg_sqr;
    end
    ...
    // set_sequencer
    foreach(subenv[i]) begin
      if(reg_block_bios[i].get_parent() == null) begin
        reg2pcie_adapter reg2pcie = new();
        //reg_block_bios[i].default_map.set_sequencer(this.h_sqr.cfg_sqr, reg2pcie);
        reg_block_bios[i].default_map.set_sequencer(subenv[i].cfg_agt.cfg_sqr, reg2pcie);
        reg_block_bios[i].default_map.set_auto_predict(1);
      end
    end
    ...
  endfucntion:connect_phase

 

 

The VCS reports that "Null object access" error. I found that the model in bios_r_seq is null. But the model of bios_r_seq in test.sv is not null. Does anybody have some experience?

 

Thanks in advance. 

[mrforever]

Hi, did anybody meet the similar problem?

[myym]

Hi,

 

I had a similar problem.

 

Althou everything seems running, but, I don't see tthe bar-0 mapped MWr/MRd packets, The Cadence's Denali PCIe UVM VIP complained ATS and I did set the ATS (Address Translation == 0) in the randomization of the reg2pcie_adapter. But, again, I don't see the packet at the pcie bus. Sigh!!!

I suspect that it's from my reg2pcie_adapter.sv code. What did I do wrong?

 

Anyone has a better reg2pcie_adapter.sv code.

 

Highly appreciated.

Rgds,

myym