-
Content Count
90 -
Joined
-
Last visited
About Roman
-
Rank
Member
Profile Information
-
Gender
Not Telling
-
Hermanmeds reacted to a post in a topic: DVClub Shanghai (China) Event: Experiences of Using UVM -- Registration Open!!
-
Hermanmeds reacted to a post in a topic: DVClub Shanghai (China) Event: Experiences of Using UVM -- Registration Open!!
-
uvm-1.2 uvm_dpi.cc compile errors using questasim 10.2c
Roman replied to Roman's topic in UVM Simulator Specific Issues
Hi Dave, I tried your new Makefile.questa, but QuestaSim 10.2c could not work both on Linux version (32bits mode in Makefile) and on Win7_64 OS with Cygwin64 tool (64bits mode in Makefile / gcc-4.5.0-mingw64). Here are the full error messages. 1. The errors in QuestaSim vlog 10.2c Linux version with 32bits vlib work vlog -timescale "1ns/1ns" ../../../../src/dpi/uvm_dpi.cc -ccflags -DQUESTA -writetoplevels questa.tops +incdir+../../../../src ../../../../src/uvm.sv +incdir+. \ top.sv QuestaSim vlog 10.2c Compiler 2013.07 Jul 18 2013 -- Compiling package uvm_pkg ** Warning: ../../.. -
uvm-1.2 uvm_dpi.cc compile errors using questasim 10.2c
Roman replied to Roman's topic in UVM Simulator Specific Issues
Hi Dave, Above question is based on linux version. My friend also tired the Questa Sim-64 10.2c win64 to compile the UVM-1.2 example. but he met following error. do you have any suggestion? [Administrator@PC201408061944 ...sequence/basic_read_write_sequence]$ make -f Makefile.questa all make -f Makefile.questa LIBNAME=uvm_dpi BITS=64 dpi_libWin make[1]: Entering directory '/home/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib d:/questasim64_10.2c/gcc-4.5.0-mingw64/bin/g++.exe -g -DQUESTA -W -shared -Bsymbolic -Id:/questasim64_10.2c/include -I../../ -
uvm-1.2 uvm_dpi.cc compile errors using questasim 10.2c
Roman replied to Roman's topic in UVM Simulator Specific Issues
Thanks Dave. The story of this case is that my friends asked me why Mentor's simulator could not work for UVM-1.2 built-in example, but other vendors could do that without any changes. You know, everyone is going to try the UVM-1.2 example and we are also on the migration way. I also tried to change the gcc to MTI install dir as following changes in Makefile.questa, however I meet the same compile errors. GCC = $(MTI_HOME)/gcc-4.5.0-linux/bin/g++ Do you have any other suggestions? Thanks! cybvgar-nx23:/home/romwang/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_se -
I met following issue in UVM-1.2 built-in example, but it could work well in UVM-1.1d. questasim 10.3c is the same. Are these versions not supporting UVM-1.2? cybvgar-nx23:/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence% m Makefile.questa all make -f Makefile.questa BITS=32 dpi_lib make[1]: Entering directory `/home/uvm/uvm-1.2/examples/simple/sequence/basic_read_write_sequence' mkdir -p ../../../../lib gcc -m32 -fPIC -DQUESTA -g -W -shared -x c -I/tool/cbar/apps/questa/10.2c/questasim/include ../../../../src/dpi/uvm_dpi.cc -o ../../../../lib/uvm_dpi.so In file
-
do set_auto_predict(0) because you are using explicit prediction infrastructure.
-
How to override set_timeout
Roman replied to karandeep963's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Supposed different test could have a little different command line options beside UVM_TESTNAME, then you could also control the timeout via uvm_comandline using "+UVM_TIMEOUT=<timeout>,<overridable>" -
Hi, #1. when you call the UVM_REG.write, the bus2reg happens twice. It's correct. 1st happens on uvm_reg_map::do_bus_write (adapter.bus2reg(bus_rsp/req,rw_access) 2nd happens on uvm_reg_predictor::write( adapter.bus2reg(tr,rw) ---- when bus monitor broadcasts the bus transaction (write or read) to uvm_reg_predictor.bus_in, this function will be called and will update the RAL model. #2. Make sure your bus monitor connects to the uvm_reg_predictor.bus_in uvm_analysis_imp well. please also check if the read data is 0 or correct value on the bus of DUT. Try block_obj.reg2.get_m
-
Update Mentor’s new links to the event. Check it out. http://www.mentorg.com.cn http://www.mentorg.com.cn/aboutus/event_info.php?id=15&s=hyjs http://www.linkedin.com/groups/DVClub-Shanghai-Experiences-Using-UVM-4668056.S.5851471572233117700?view=&gid=4668056&type=member&item=5851471572233117700&trk=eml-anet_dig-b_nd-pst_ttle-cn Posted in Verification Horizons eNewsLetter
-
lisakb1963 reacted to a post in a topic: We named our new dog UVM
-
Event: Experiences of Using UVM - DVClub Shanghai Date: 28 March 2014 Time: 14.40 to 17.30 (CST) 07.00 to 09.30 (GMT) Organizer: Mike Bartley @TVS Roman Wang @AMD Charles Sun @Topbrian Sponsors: ARM, Cadence, Mentor and Synopsys The next DVClub Shanghai webcast event takes place on Friday, 28th March and will focus on the experience of UVM! Why not register to hear five speakers bringing their own unique perspective: Agenda (CST) 14.40 Arrival and Networking 15.00 Mike Bartley, Test and Verification Solutions - Verification Challange Outlook in 2014 15.30 Uwe
-
We named our new dog UVM
Roman replied to nosnhojn's topic in UVM (Pre-IEEE) Methodology and BCL Forum
She is nice and I love her, however she bites me everyday. -
How to verify reset processing with UVM?
Roman replied to nslmike's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I believe follow topic could address your problem well. "Resetting Your UVM SystemVerilog Environment in the Middle of a Test — Introducing the UVM Reset Package" http://www.cadence.com/Community/blogs/fv/archive/2014/02/26/resetting-your-uvm-sytemverilog-environment-in-the-middle-of-a-test-_2D00_-introducing-the-uvm-reset-package.aspx -
adding delay between regmodel transactions
Roman replied to phil's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi Phil, I think you'd better add the random delay on the iUVC's Driver. (iUVC = Interface UVC) between transaction.. As we know, reg item from UVM REG will be translated to bus item by UVM REG Layering, and iUVC's Driver will drive the bus. UVM REG model is just designed to facilitate productive verification of SW programmable HW. I don't think it's better to implement random on the UVM REG model.