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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. How to determine if a UVM_REG is initialized

    By wdwhiteh,
    • 0 replies
    • 833 views

  2. uvm_reg_field::do_predict() does not call cb.post_predict for UVM_PREDICT_DIRECT

    By wdwhiteh,
    • 0 replies
    • 1.4k views

  3. different between run_phase and other 12 runtime phase

    By qinhailiang,
    • 2 replies
    • 4k views

  4. Unused bits in a uvm_reg

    By ejo,
    • 7 replies
    • 2.8k views

  5. Modifycation of uvm_object internals

    By josefj,
    • 3 replies
    • 2k views

  6. System level uvm_reg_map::get_n_bytes() returns 0?

    By Logger,   
    • 0 replies
    • 1.5k views

  7. creating sequence library of virtual sequences

    By akshaykasodariya,   
    • 1 reply
    • 2.3k views

  8. sequencer and sequence driver

    By antwens,
    • 1 reply
    • 1.2k views

  9. Implementing register burst read

    By ejo,
    • 0 replies
    • 1.2k views

  10. Hierarchical register maps

    By Witty,
    • 0 replies
    • 1.2k views

  11. Why is there no uvm_reg_block::write_field_by_name()?

    By nguthrie,
    • 7 replies
    • 3.6k views

  12. Writing register fields

    By ejo,
    • 0 replies
    • 3.9k views

  13. bidir TLM ports

    By Logger,
    • 1 reply
    • 1.9k views

  14. UVM_MEM bursting

    By rams0053,   
    • 0 replies
    • 1.4k views

  15. set_rights for uvm reg

    By McPall,   
    • 1 reply
    • 1.9k views

  16. Interface Monitor implementation

    By paragsathe,   
    • 0 replies
    • 2.4k views

  17. 16-bit uvm_mem in 32-bit map - overlap warning

    By bwirth,
    • 0 replies
    • 1.4k views

  18. Notify scoreboard about memory accesses

    By ofird,
    • 0 replies
    • 2.5k views

  19. uvm supports vera verification env

    By zheng,
    • 0 replies
    • 960 views

  20. UVM 1.2 , run_phase deprecation, and pre-compiling uvm base class

    By ljepson74,   
    • 2 replies
    • 2.4k views

  21. Disable UVM_INFO printout by verbosity

    By drianf0,
    • 1 reply
    • 6.1k views

  22. Of begin_event, end_event, transaction recording, and pipelined interfaces

    By Logger,
    • 3 replies
    • 9.1k views

  23. Controlling verbosity while using component override

    By akshaykasodariya,   
    • 4 replies
    • 2.2k views

  24. Multiple CPU interfaces can access the same register model

    By ofird,
    • 2 replies
    • 2.1k views

  25. What ever you do, don't use ...

    By chrisspear,
    • 8 replies
    • 5.8k views
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