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uvm reg limitation

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I don't think there is any hard limitation in place. You just instantiate as many registers as you want. There are no fixed size arrays for the registers to go into. You are, probably, limited by the hardware you're simulating on (i.e. memory), but this has nothing to do with UVM RAL itself.

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  • 2 weeks later...



there should be no limitations affecting you. there might be simulator limitations (size of arrays etc.) but even those are far away. the typical bounds for the register model are defined by the number of types (registers, registerfiles,...) and instances for compile/elab/simulation. these are soft (=handling) bounds (memory+time) rather then implementation bounds.



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