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  1. can you please tell how to verify using only 1 agent. in different kinds of interfaces are present, diff agents are to be taken right? host and can interfaces are different. so atleast 2 are needed. how to do with 1agent?
  2. using one agent how can i verify a can controller. i'm thinking that i should have atleast 2 agents. 1 agent is with microprocessor interface used to program can controller and send data to can controller by puttting data into transmit buffer. 1 agent is with can interface used as other node in can bus network. if i have more nodes (suppose 5) i'm think i should have 5 agents with can interface. is my understanding correct.
  3. in can controller we have many sub modules like acceptance filter registers frame generators synchronizers etc... how to create verification env for it. do i need to verify all these sub components using uvm env only or seperately. each can controller acts as master and slave, if i have 4 can nodes, how many agents are required and does each node have both master and slave capabilities.
  4. ejo can you please suggest any example for this so that i can get clear idea
  5. suppose my design is having fifos,counters and logic for some complex algorithm. using uvm i can create agents to test signals in interfaces. how to verify internal fifos using uvm environment? do i need to verify seperately?
  6. i have a sequence lib. i created a base_seq in which i used pre_body() and post_body() to raise and drop objections. but my code is not executing pre and post body. im getting an error indicating time out. how can i resolve it. all the sequences extending base_seq must raise and drop objection.........
  7. suppose i have to develop top,test,env1,env2,both env has 2 agents which are active,agents and env have to be configured. now plese tell me the order in which i should start developing my uvm testbench. at the first stage do i need to put exact tests and configuration or just put messages and then start developing from sequence item,sequences,driver,monitor,agent,env....
  8. i have understood all topics of uvm but i am not understanding how to start uvm testbench. do i need to develop test module first or do i need to start from uvm_sequence_item ,then uvm_sequences,sequencer,driver,monitor,agent.... my question is do i need to develop testbench from top to bottom or from bottom to top? at each stage i want to check whether developed code is correct or not. how can i do it? suppose i develop a sequence item ,i can randomize and check various patterns generated. but if i would like to check driver or monitor or sequencer or any other component of uvm ,what method should be followed. thankyou.................
  9. by default when a numerical value is printed, it is displayed as hexa decimal. how can i change it to decimal using print(). eg; class mycls extends uvm_sequence_item; int a,b,c; endclass in top module........ mycls m1=new; m1.print(); above displays a,b,c in hexa. how to change to decimal?
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