Search the Community
Showing results for tags 'time step'.
As used in the SystemVerilog LRM, 1800.1-2017.pdf, what is the difference between these two terms? The first seems well defined. The second, not so much. * time slot * time step Cliff Cummings/Sunburst Design wrote the following in CummingsSNUG2006Boston_SystemVerilog_Events.pdf: If that is correct, then it seems the term 'time step' has returned.
I am currently working on a module that equidistantly reads in values from a text file. For this purpose, I use the file_in_tdf module from the basic library of COSIDE and have set the time step to 1s and interpolation to true. The idea now is to have a subsequent module that, however, has a lower time step, let's say 10 ms. Unfortunately I get the following error when trying to simulate: Inconsistency in timestep assignment between module: top. ... .i_file_in_tdf1 timestep: 1 s (1 Hz) expect: 10 ms (100 Hz) and module: top. ... .dummy_inst T: 10 ms (100 Hz) or expect: 1 s (1 Hz)