reg.randomize doesn't work for some regs

[Weicai]

In uvm_reg_field::configure, UVM turns off rand_mode for some regs.

   // Ignore is_rand if the field is known not to be writeable
   // i.e. not "RW", "WRC", "WRS", "WO", "W1", "WO1"
   case (access)
    "RO", "RC", "RS", "WC", "WS",
      "W1C", "W1S", "W1T", "W0C", "W0S", "W0T",
      "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS",
      "WOC", "WOS": is_rand = 0;
   endcase

   if (!is_rand)
     value.rand_mode(0);

https://verificationacademy.com/verification-methodology-reference/uvm/src/reg/uvm_reg_field.svh

We have a W0C reg. I use this to randomize and update it. And it always writes default value to the reg, which took me a while to figure it out.

csr.randomize();
csr.update();

I don't agree with the comment in UVM. "RO" isn't writeable, but it's good to write some value and test it. "W1C", "W0C" and some others are writeable.
I feel it's not right to set rand_mode=0 for these types of regs. Not sure what the motivation of doing this is.

We also discuss this here https://github.com/lowRISC/opentitan/issues/5105

 

Thanks

Weicai