Thomas Kruse Posted February 25, 2021 Report Share Posted February 25, 2021 Because of the increasing number of parametrized designs, is there a definition for the behavior of the reduction operators in SystemVerilog if the input vector is just one bit? module reduction #( in_c = 1 ) ( input logic [in_c-1:0] i, output logic o1, o2, o3 ); assign o1 = &i; assign o2 = |i; assign o3 = ^i; endmodule Thanks Thomas Quote Link to comment Share on other sites More sharing options...
dave_59 Posted February 25, 2021 Report Share Posted February 25, 2021 This is a open issue with the LRM. https://accellera.mantishub.io/view.php?id=7190 Quote Link to comment Share on other sites More sharing options...
Thomas Kruse Posted February 25, 2021 Author Report Share Posted February 25, 2021 Thanks, Dave! Best regards, Thomas Quote Link to comment Share on other sites More sharing options...
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