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Reduction operator in case of one-bit vector

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Because of the increasing number of parametrized designs, is there a definition for the behavior of the reduction operators in SystemVerilog if the input vector is just one bit? 

module reduction
    in_c = 1
    input logic [in_c-1:0] i,
    output logic o1, o2, o3
  assign o1 = &i;
  assign o2 = |i;
  assign o3 = ^i;



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