Reduction operator in case of one-bit vector

[Thomas Kruse]

Because of the increasing number of parametrized designs, is there a definition for the behavior of the reduction operators in SystemVerilog if the input vector is just one bit? 

module reduction
  #(
    in_c = 1
  )
  (
    input logic [in_c-1:0] i,
    output logic o1, o2, o3
  );
  assign o1 = &i;
  assign o2 = |i;
  assign o3 = ^i;
endmodule

Thanks

   Thomas

[dave_59]

This is a open issue with the LRM. https://accellera.mantishub.io/view.php?id=7190

[Thomas Kruse]

Thanks, Dave!

Best regards,

   Thomas