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The question on reactive slave
VVdemajia posted a topic in UVM SystemVerilog DiscussionsI am a new comer on UVM, and have a question on reactive slave agent. I saw the reactive slave agent sample in $UVM_HOME/example/ubus/. It has the mechanism includes sequence/sequencer/drive. I know the memory model is inside in the sequence, and the read data is sent back as resp to DUT. I have a question that if I integrate in the driver, do I still need the sequence and sequencer in the reactive slave ? I feel like keep the reactive slave agent including all of these is better to let the agent more flexible and extension. The sequence can change the response can change it and not only store it. Is it right for my understanding ?