Jump to content

SystemVerilog Assertions not getting included


Recommended Posts

Folks,

Due to some scripting issues, we were not able to bind our SVA files. Since there was no compile issues and no assertions were included(and were not firing), it got undetected for few days.

Without doing manual inspection, is there a way to make sure that we include assertion files. Only thing I can think of is to write a script to cross check, but if name changes etc happens you have to keep maintaining the script.

Any suggestions?

Thanks

-Ankit

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...