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SystemVerilog Assertions not getting included

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Due to some scripting issues, we were not able to bind our SVA files. Since there was no compile issues and no assertions were included(and were not firing), it got undetected for few days.

Without doing manual inspection, is there a way to make sure that we include assertion files. Only thing I can think of is to write a script to cross check, but if name changes etc happens you have to keep maintaining the script.

Any suggestions?



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