UVM Simulator Specific Issues

173 topics in this forum

1. Free systemverilog/uvm simulator for small amounts of code exists?

   By ljepson74, May 30, 2013   

   • simulator
   • great question
   • (and 1 more)

     Tagged with:

     • simulator
     • great question
     • free
   • 13 replies
   • 21,080 views
   • 
   • David Black
   • July 27

2. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

   By swapnilm, February 5, 2013
   • 6 replies
   • 5,051 views
   • 
   • David Black
   • July 13

3. uvm hdl force and simulator optimization

   By wwen, January 22
   • 0 replies
   • 102 views
   • 
   • wwen
   • January 22

4. savl

   By SVv, November 26, 2019
   • 2 replies
   • 138 views
   • 
   • David Black
   • November 26, 2019

5. SystemVerilog/UVM linting - what tools exist ?

   By ljepson74, March 3, 2015   

   • lint
   • 5 replies
   • 3,989 views
   • 
   • rgarciaf071
   • September 9, 2019

6. Failed to find 'create_item' in hierarchical name /create_item !!!

   By qinhailiang, June 13, 2011
   • 1 reply
   • 3,037 views
   • 
   • Ranaa
   • October 17, 2018

7. How can I record the transaction of UVM by irun?

   By u24c02, September 21, 2018
   • 0 replies
   • 874 views
   • 
   • u24c02
   • September 21, 2018

8. BKM - Using Cadence Incisive with UVM?

   By cliffc, December 12, 2012
   • 3 replies
   • 8,637 views
   • 
   • Prawin
   • September 20, 2018

9. uvm-1.2 example compile error

   By u24c02, September 13, 2018
   • 1 reply
   • 1,092 views
   • 
   • uwes
   • September 17, 2018

10. How can I dump waveform using irun uder UVM environment?

    By u24c02, September 13, 2018
    • 0 replies
    • 511 views
    • 
    • u24c02
    • September 13, 2018

11. UVM-ML connecting SystemC ports

    By Khushi, August 1, 2018
    • 0 replies
    • 387 views
    • 
    • Khushi
    • August 1, 2018

12. Changes in generic paylod are not reflected in UVM side

    By Khushi, July 19, 2018
    • 0 replies
    • 275 views
    • 
    • Khushi
    • July 19, 2018

13. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan, April 3, 2018
    • 0 replies
    • 1,141 views
    • 
    • mooredan
    • April 3, 2018

14. Connect interface to dut

    By fbochud, September 5, 2013
    • 7 replies
    • 8,206 views
    • 
    • dave_59
    • December 21, 2017

15. How do I make multiple burst on systemverilog?

    By u24c02, December 4, 2017
    • 0 replies
    • 807 views
    • 
    • u24c02
    • December 4, 2017

16. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02, November 30, 2017
    • 0 replies
    • 459 views
    • 
    • u24c02
    • November 30, 2017

17. Unrecognized system task or function: $cdn_ahb_access

    By u24c02, November 28, 2017
    • 2 replies
    • 802 views
    • 
    • u24c02
    • November 28, 2017

18. ERROR IN NCSIM Simulation -E,CUVMUR

    By Venkatesh, April 21, 2017
    • 1 reply
    • 6,179 views
    • 
    • kurtlin
    • April 22, 2017

19. vpi_user.h : file or directory not found

    By lucaspeixotot, January 7, 2017   

    • vpi user
    • 1 reply
    • 2,162 views
    • 
    • tudor.timi
    • February 17, 2017

20. unexpected behavior of incisiv with disable in for loop

    By shubham_dce, January 15, 2017   

    • incisiv
    • rtl
    • 2 replies
    • 819 views
    • 
    • shubham_dce
    • January 18, 2017

21. VCS implementation of register bitbash sequence

    By chethandn, January 16, 2017   

    • uvm
    • ral
    • (and 1 more)

      Tagged with:

      • uvm
      • ral
      • bitbash
    • 0 replies
    • 2,374 views
    • 
    • chethandn
    • January 16, 2017

22. UVM-Connect 2.3.0 Example Not Compiling for me

    By mingchu, December 13, 2016   

    • uvm
    • systemc
    • (and 3 more)

      Tagged with:

      • uvm
      • systemc
      • uvmc
      • vcs
      • systemverilog
    • 0 replies
    • 974 views
    • 
    • mingchu
    • December 13, 2016

23. How to check VCS version number?

    By ljepson74, July 22, 2016   

    • vcs
    • version
    • 3 replies
    • 14,437 views
    • 
    • Gowri Sankar
    • September 1, 2016

24. VCS running multiple top modules - simulate just one?

    By cliffc, December 1, 2015   

    • vcs
    • verilog
    • (and 2 more)

      Tagged with:

      • vcs
      • verilog
      • top
      • module
    • 1 reply
    • 4,760 views
    • 
    • sri.cvcblr
    • January 7, 2016

25. Cadence IPXact -> UVM_REG Register Map generator

    By anthony.winter, June 30, 2011
    • 6 replies
    • 10,526 views
    • 
    • viru_agnisys
    • December 14, 2015