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UVM Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

180 topics in this forum

  1. UVM1.2 with modelsim 2021.4

    By chirowuvm,
    • 1 reply
    • 528 views

  2. UVM in Python

    By Ameen Raza Khan,   
    • 0 replies
    • 208 views

  3. Error: Null Object access

    By Meghana K,
    • 1 reply
    • 640 views

  4. Error: Cross-module reference resolution error

    By Abdul Razak H S,
    • 0 replies
    • 1.6k views

  5. Geting started error on Cadence (Multiple packages)

    By EugenueY,
    • 7 replies
    • 13.5k views

  6. Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "me.new.this" from module "\package uvm_1_2.uvm_pkg\

    By nasirkhanpak25,
    • 0 replies
    • 499 views

  7. Synopsys VCS: Compilation Error when running example from UVM1.0 package

    By Jay,
    • 2 replies
    • 13.4k views

  8. VCS run option to use random seed?

    By ljepson74,
    • 2 replies
    • 4.8k views

  9. VCS 2019.06 strong and weak support

    By ljepson74,
    • 4 replies
    • 2.6k views

  10. Free systemverilog/uvm simulator for small amounts of code exists?

    By ljepson74,   
    • 13 replies
    • 24.8k views

  11. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

    By swapnilm,
    • 6 replies
    • 6.5k views

  12. uvm hdl force and simulator optimization

    By wwen,
    • 0 replies
    • 940 views

  13. savl

    By SVv,
    • 2 replies
    • 1.2k views

  14. SystemVerilog/UVM linting - what tools exist ?

    By ljepson74,   
    • 5 replies
    • 5.5k views

  15. Failed to find 'create_item' in hierarchical name /create_item !!!

    By qinhailiang,
    • 1 reply
    • 3.9k views

  16. How can I record the transaction of UVM by irun?

    By u24c02,
    • 0 replies
    • 2.4k views

  17. BKM - Using Cadence Incisive with UVM?

    By cliffc,
    • 3 replies
    • 11.1k views

  18. uvm-1.2 example compile error

    By u24c02,
    • 1 reply
    • 4k views

  19. How can I dump waveform using irun uder UVM environment?

    By u24c02,
    • 0 replies
    • 1.1k views

  20. UVM-ML connecting SystemC ports

    By Khushi,
    • 0 replies
    • 877 views

  21. Changes in generic paylod are not reflected in UVM side

    By Khushi,
    • 0 replies
    • 672 views

  22. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan,
    • 0 replies
    • 2.9k views

  23. Connect interface to dut

    By fbochud,
    • 7 replies
    • 11k views

  24. How do I make multiple burst on systemverilog?

    By u24c02,
    • 0 replies
    • 1.7k views

  25. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02,
    • 0 replies
    • 826 views
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