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UVM Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

178 topics in this forum

  1. Error: Null Object access

    By Meghana K,
    • 1 reply
    • 17 views

  2. Error: Cross-module reference resolution error

    By Abdul Razak H S,
    • 0 replies
    • 31 views

  3. Geting started error on Cadence (Multiple packages)

    By EugenueY,
    • 7 replies
    • 11.9k views

  4. Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "me.new.this" from module "\package uvm_1_2.uvm_pkg\

    By nasirkhanpak25,
    • 0 replies
    • 181 views

  5. Synopsys VCS: Compilation Error when running example from UVM1.0 package

    By Jay,
    • 2 replies
    • 11.8k views

  6. VCS run option to use random seed?

    By ljepson74,
    • 2 replies
    • 2.2k views

  7. VCS 2019.06 strong and weak support

    By ljepson74,
    • 4 replies
    • 1.4k views

  8. Free systemverilog/uvm simulator for small amounts of code exists?

    By ljepson74,   
    • 13 replies
    • 23.4k views

  9. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

    By swapnilm,
    • 6 replies
    • 5.8k views

  10. uvm hdl force and simulator optimization

    By wwen,
    • 0 replies
    • 632 views

  11. savl

    By SVv,
    • 2 replies
    • 639 views

  12. SystemVerilog/UVM linting - what tools exist ?

    By ljepson74,   
    • 5 replies
    • 4.9k views

  13. Failed to find 'create_item' in hierarchical name /create_item !!!

    By qinhailiang,
    • 1 reply
    • 3.5k views

  14. How can I record the transaction of UVM by irun?

    By u24c02,
    • 0 replies
    • 1.7k views

  15. BKM - Using Cadence Incisive with UVM?

    By cliffc,
    • 3 replies
    • 10.2k views

  16. uvm-1.2 example compile error

    By u24c02,
    • 1 reply
    • 2.6k views

  17. How can I dump waveform using irun uder UVM environment?

    By u24c02,
    • 0 replies
    • 834 views

  18. UVM-ML connecting SystemC ports

    By Khushi,
    • 0 replies
    • 591 views

  19. Changes in generic paylod are not reflected in UVM side

    By Khushi,
    • 0 replies
    • 459 views

  20. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan,
    • 0 replies
    • 2.2k views

  21. Connect interface to dut

    By fbochud,
    • 7 replies
    • 9.9k views

  22. How do I make multiple burst on systemverilog?

    By u24c02,
    • 0 replies
    • 1.2k views

  23. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02,
    • 0 replies
    • 657 views

  24. Unrecognized system task or function: $cdn_ahb_access

    By u24c02,
    • 2 replies
    • 1.3k views

  25. ERROR IN NCSIM Simulation -E,CUVMUR

    By Venkatesh,
    • 1 reply
    • 10.5k views
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