UVM Simulator Specific Issues

175 topics in this forum

1. Synopsys VCS: Compilation Error when running example from UVM1.0 package

   By Jay, November 18, 2011
   • 2 replies
   • 10.3k views
   • 
   • oliver
   • February 25

2. VCS run option to use random seed?

   By ljepson74, August 23, 2020
   • 2 replies
   • 904 views
   • 
   • sri.cvcblr
   • January 2

3. Geting started error on Cadence (Multiple packages)

   By EugenueY, July 16, 2012
   • 6 replies
   • 10.5k views
   • 
   • arjunmenonk
   • September 24, 2020

4. VCS 2019.06 strong and weak support

   By ljepson74, August 25, 2020
   • 4 replies
   • 696 views
   • 
   • ljepson74
   • August 27, 2020

5. Free systemverilog/uvm simulator for small amounts of code exists?

   By ljepson74, May 30, 2013   

   • simulator
   • great question
   • (and 1 more)

     Tagged with:

     • simulator
     • great question
     • free
   • 13 replies
   • 22.1k views
   • 
   • David Black
   • July 27, 2020

6. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

   By swapnilm, February 5, 2013
   • 6 replies
   • 5.5k views
   • 
   • David Black
   • July 13, 2020

7. uvm hdl force and simulator optimization

   By wwen, January 22, 2020
   • 0 replies
   • 408 views
   • 
   • wwen
   • January 22, 2020

8. savl

   By SVv, November 26, 2019
   • 2 replies
   • 410 views
   • 
   • David Black
   • November 26, 2019

9. SystemVerilog/UVM linting - what tools exist ?

   By ljepson74, March 3, 2015   

   • lint
   • 5 replies
   • 4.5k views
   • 
   • rgarciaf071
   • September 9, 2019

10. Failed to find 'create_item' in hierarchical name /create_item !!!

    By qinhailiang, June 13, 2011
    • 1 reply
    • 3.3k views
    • 
    • Ranaa
    • October 17, 2018

11. How can I record the transaction of UVM by irun?

    By u24c02, September 21, 2018
    • 0 replies
    • 1.3k views
    • 
    • u24c02
    • September 21, 2018

12. BKM - Using Cadence Incisive with UVM?

    By cliffc, December 12, 2012
    • 3 replies
    • 9.7k views
    • 
    • Prawin
    • September 20, 2018

13. uvm-1.2 example compile error

    By u24c02, September 13, 2018
    • 1 reply
    • 1.7k views
    • 
    • uwes
    • September 17, 2018

14. How can I dump waveform using irun uder UVM environment?

    By u24c02, September 13, 2018
    • 0 replies
    • 685 views
    • 
    • u24c02
    • September 13, 2018

15. UVM-ML connecting SystemC ports

    By Khushi, August 1, 2018
    • 0 replies
    • 495 views
    • 
    • Khushi
    • August 1, 2018

16. Changes in generic paylod are not reflected in UVM side

    By Khushi, July 19, 2018
    • 0 replies
    • 374 views
    • 
    • Khushi
    • July 19, 2018

17. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan, April 3, 2018
    • 0 replies
    • 1.7k views
    • 
    • mooredan
    • April 3, 2018

18. Connect interface to dut

    By fbochud, September 5, 2013
    • 7 replies
    • 9k views
    • 
    • dave_59
    • December 21, 2017

19. How do I make multiple burst on systemverilog?

    By u24c02, December 4, 2017
    • 0 replies
    • 1k views
    • 
    • u24c02
    • December 4, 2017

20. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02, November 30, 2017
    • 0 replies
    • 576 views
    • 
    • u24c02
    • November 30, 2017

21. Unrecognized system task or function: $cdn_ahb_access

    By u24c02, November 28, 2017
    • 2 replies
    • 1k views
    • 
    • u24c02
    • November 28, 2017

22. ERROR IN NCSIM Simulation -E,CUVMUR

    By Venkatesh, April 21, 2017
    • 1 reply
    • 8.4k views
    • 
    • kurtlin
    • April 22, 2017

23. vpi_user.h : file or directory not found

    By lucaspeixotot, January 7, 2017   

    • vpi user
    • 1 reply
    • 2.8k views
    • 
    • tudor.timi
    • February 17, 2017

24. unexpected behavior of incisiv with disable in for loop

    By shubham_dce, January 15, 2017   

    • incisiv
    • rtl
    • 2 replies
    • 922 views
    • 
    • shubham_dce
    • January 18, 2017

25. VCS implementation of register bitbash sequence

    By chethandn, January 16, 2017   

    • uvm
    • ral
    • (and 1 more)

      Tagged with:

      • uvm
      • ral
      • bitbash
    • 0 replies
    • 2.5k views
    • 
    • chethandn
    • January 16, 2017