Jump to content

UVM Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

176 topics in this forum

  1. Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "me.new.this" from module "\package uvm_1_2.uvm_pkg\

    By nasirkhanpak25,
    • 0 replies
    • 26 views

  2. Synopsys VCS: Compilation Error when running example from UVM1.0 package

    By Jay,
    • 2 replies
    • 10.9k views

  3. VCS run option to use random seed?

    By ljepson74,
    • 2 replies
    • 1.3k views

  4. Geting started error on Cadence (Multiple packages)

    By EugenueY,
    • 6 replies
    • 10.9k views

  5. VCS 2019.06 strong and weak support

    By ljepson74,
    • 4 replies
    • 931 views

  6. Free systemverilog/uvm simulator for small amounts of code exists?

    By ljepson74,   
    • 13 replies
    • 22.4k views

  7. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

    By swapnilm,
    • 6 replies
    • 5.6k views

  8. uvm hdl force and simulator optimization

    By wwen,
    • 0 replies
    • 481 views

  9. savl

    By SVv,
    • 2 replies
    • 498 views

  10. SystemVerilog/UVM linting - what tools exist ?

    By ljepson74,   
    • 5 replies
    • 4.6k views

  11. Failed to find 'create_item' in hierarchical name /create_item !!!

    By qinhailiang,
    • 1 reply
    • 3.4k views

  12. How can I record the transaction of UVM by irun?

    By u24c02,
    • 0 replies
    • 1.4k views

  13. BKM - Using Cadence Incisive with UVM?

    By cliffc,
    • 3 replies
    • 9.9k views

  14. uvm-1.2 example compile error

    By u24c02,
    • 1 reply
    • 1.9k views

  15. How can I dump waveform using irun uder UVM environment?

    By u24c02,
    • 0 replies
    • 723 views

  16. UVM-ML connecting SystemC ports

    By Khushi,
    • 0 replies
    • 521 views

  17. Changes in generic paylod are not reflected in UVM side

    By Khushi,
    • 0 replies
    • 394 views

  18. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan,
    • 0 replies
    • 1.9k views

  19. Connect interface to dut

    By fbochud,
    • 7 replies
    • 9.2k views

  20. How do I make multiple burst on systemverilog?

    By u24c02,
    • 0 replies
    • 1.1k views

  21. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02,
    • 0 replies
    • 600 views

  22. Unrecognized system task or function: $cdn_ahb_access

    By u24c02,
    • 2 replies
    • 1.1k views

  23. ERROR IN NCSIM Simulation -E,CUVMUR

    By Venkatesh,
    • 1 reply
    • 9k views

  24. vpi_user.h : file or directory not found

    By lucaspeixotot,   
    • 1 reply
    • 3k views

  25. unexpected behavior of incisiv with disable in for loop

    By shubham_dce,   
    • 2 replies
    • 943 views
×
×
  • Create New...