UVM Simulator Specific Issues

180 topics in this forum

1. UVM1.2 with modelsim 2021.4

   By chirowuvm, July 19
   • 1 reply
   • 138 views
   • 
   • dave_59
   • July 28

2. UVM in Python

   By Ameen Raza Khan, July 2   

   • uvm
   • python
   • (and 1 more)

     Tagged with:

     • uvm
     • python
     • makefile
   • 0 replies
   • 96 views
   • 
   • Ameen Raza Khan
   • July 2

3. Error: Null Object access

   By Meghana K, May 27
   • 1 reply
   • 205 views
   • 
   • David Black
   • May 27

4. Error: Cross-module reference resolution error

   By Abdul Razak H S, May 26
   • 0 replies
   • 234 views
   • 
   • Abdul Razak H S
   • May 26

5. Geting started error on Cadence (Multiple packages)

   By EugenueY, July 16, 2012
   • 7 replies
   • 12.4k views
   • 
   • prase
   • December 16, 2021

6. Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "me.new.this" from module "\package uvm_1_2.uvm_pkg\

   By nasirkhanpak25, October 20, 2021
   • 0 replies
   • 294 views
   • 
   • nasirkhanpak25
   • October 20, 2021

7. Synopsys VCS: Compilation Error when running example from UVM1.0 package

   By Jay, November 18, 2011
   • 2 replies
   • 12.3k views
   • 
   • oliver
   • February 25, 2021

8. VCS run option to use random seed?

   By ljepson74, August 23, 2020
   • 2 replies
   • 3k views
   • 
   • sri.cvcblr
   • January 2, 2021

9. VCS 2019.06 strong and weak support

   By ljepson74, August 25, 2020
   • 4 replies
   • 1.7k views
   • 
   • ljepson74
   • August 27, 2020

10. Free systemverilog/uvm simulator for small amounts of code exists?

    By ljepson74, May 30, 2013   

    • simulator
    • great question
    • (and 1 more)

      Tagged with:

      • simulator
      • great question
      • free
    • 13 replies
    • 23.8k views
    • 
    • David Black
    • July 27, 2020

11. Where to download questasim-gcc-4.2.1-mingw32vc9.zip from?

    By swapnilm, February 5, 2013
    • 6 replies
    • 6k views
    • 
    • David Black
    • July 13, 2020

12. uvm hdl force and simulator optimization

    By wwen, January 22, 2020
    • 0 replies
    • 759 views
    • 
    • wwen
    • January 22, 2020

13. savl

    By SVv, November 26, 2019
    • 2 replies
    • 769 views
    • 
    • David Black
    • November 26, 2019

14. SystemVerilog/UVM linting - what tools exist ?

    By ljepson74, March 3, 2015   

    • lint
    • 5 replies
    • 5.1k views
    • 
    • rgarciaf071
    • September 9, 2019

15. Failed to find 'create_item' in hierarchical name /create_item !!!

    By qinhailiang, June 13, 2011
    • 1 reply
    • 3.6k views
    • 
    • Ranaa
    • October 17, 2018

16. How can I record the transaction of UVM by irun?

    By u24c02, September 21, 2018
    • 0 replies
    • 1.9k views
    • 
    • u24c02
    • September 21, 2018

17. BKM - Using Cadence Incisive with UVM?

    By cliffc, December 12, 2012
    • 3 replies
    • 10.4k views
    • 
    • Prawin
    • September 20, 2018

18. uvm-1.2 example compile error

    By u24c02, September 13, 2018
    • 1 reply
    • 3.2k views
    • 
    • uwes
    • September 17, 2018

19. How can I dump waveform using irun uder UVM environment?

    By u24c02, September 13, 2018
    • 0 replies
    • 916 views
    • 
    • u24c02
    • September 13, 2018

20. UVM-ML connecting SystemC ports

    By Khushi, August 1, 2018
    • 0 replies
    • 660 views
    • 
    • Khushi
    • August 1, 2018

21. Changes in generic paylod are not reflected in UVM side

    By Khushi, July 19, 2018
    • 0 replies
    • 533 views
    • 
    • Khushi
    • July 19, 2018

22. VCS UVM_TESTNAME compile once simulate multiple in same directory

    By mooredan, April 3, 2018
    • 0 replies
    • 2.5k views
    • 
    • mooredan
    • April 3, 2018

23. Connect interface to dut

    By fbochud, September 5, 2013
    • 7 replies
    • 10.2k views
    • 
    • dave_59
    • December 21, 2017

24. How do I make multiple burst on systemverilog?

    By u24c02, December 4, 2017
    • 0 replies
    • 1.3k views
    • 
    • u24c02
    • December 4, 2017

25. how does a variable to be decided it's value without it's initialize in systemverilog?

    By u24c02, November 30, 2017
    • 0 replies
    • 723 views
    • 
    • u24c02
    • November 30, 2017