Hi all. This is my first post here and I'm learning UVM, but I'm not new to verification or SystemVerilog.
I've seen three examples of integrating uvm_reg_block objects into a test bench. two of them (jellybean and verificationacademy) create the extended uvm_reg_block object in the test object, whereas doulos creates it in the top level env (above the agent env).
For a hierarchical point of view, the latter location seems to make the most sense. However, it seems that there's a bunch of hoops to jump through to get it working. From a ease of use sense, creating it in the test ob