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UVM Simulator Specific Issues

Use this forum to discuss tool-specific usage and flow issues.

172 topics in this forum

  1. uvm_test_done.raise_objection(target_comp);

    By sudheer59,
    • 4 replies
    • 2,475 views

  2. vcs runtime error with uvm

    By mrforever,
    • 2 replies
    • 4,918 views

  3. Questasim: Problem with "paused" prompt

    By chessat2002,
    • 5 replies
    • 11,185 views

  4. Issue with single line comment in UVM Macro files

    By mpeer,
    • 3 replies
    • 1,608 views

  5. ** Fatal: Internal error on use of uvm_do_on macro With MTI 10.1c version

    By rajneeshT,
    • 2 replies
    • 1,478 views

  6. IPXACT and UVM with VCS

    By pradeey,
    • 2 replies
    • 3,922 views

  7. not able to run uvm1.1a in ius 10.20-p008.

    By chandan,
    • 4 replies
    • 4,989 views

  8. VCS and UVM Transaction Recording

    By mea1201,
    • 1 reply
    • 4,296 views

  9. does Synopsys VCS2011.03 support uvm 1.1c library?

    By mrforever,
    • 1 reply
    • 1,050 views

  10. [irun *E,MSSYSTF] when using uvm-1.1a, any suggestion and thanks!

    By SeanChou,
    • 18 replies
    • 14,566 views

  11. [UVM Connect] sccom not suports CentOS

    By SeanChou,
    • 2 replies
    • 1,262 views

  12. getting ncelab: *F,INTERR: INTERNAL EXCEPTION error when trying to run uvm1.1

    By usha,
    • 4 replies
    • 9,901 views

  13. IES 10.2 -- Using config_db to set array of interfaces

    By mea1201,
    • 6 replies
    • 5,543 views

  14. UVM_GRM with VCS

    By loveuvm,
    • 5 replies
    • 1,439 views

  15. How to do coverage in UVM

    By anubhaw2004,
    • 5 replies
    • 7,956 views

  16. Geting started error on Cadence (Multiple packages)

    By EugenueY,
    • 5 replies
    • 8,274 views

  17. Function uvm_hdl_deposit not found

    By debapriya,
    • 1 reply
    • 2,369 views

  18. [not related to UVM] How to find and solve the eval order dependent coding in DUT?

    By SeanChou,
    • 2 replies
    • 1,121 views

  19. Simulation blocked at waiting statement in main_phase

    By jhpark,
    • 1 reply
    • 2,552 views

  20. Error loading design during QuestaSim simulation of VHDL Design with SystemVerilog TB

    By pratyaksharn,
    • 2 replies
    • 6,835 views

  21. IUS92 SV support:

    By shidb02,
    • 3 replies
    • 1,356 views

  22. VCS MX and UVM

    By krb,
    • 3 replies
    • 13,346 views

  23. ask for help: how to dump fsdb in UVM environment with IUS simulator ?

    By Tommy_SH,
    • 4 replies
    • 6,180 views

  24. How to invoke a UVM based simulation using three step mode rather than irun

    By Roman,
    • 0 replies
    • 2,436 views

  25. lint and uvm

    By fbochud,
    • 2 replies
    • 2,662 views
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