Khushi Posted August 1, 2018 Report Share Posted August 1, 2018 Hi In UVM_ML, how to connect the following ports (from SystemC-TLM model to rest of the UVM verification env) - sc_in<int> - sc_out<bool> -sc_port<my_if<T1>> - sc_export<my_if<T1>> Thanks Quote Link to comment Share on other sites More sharing options...
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