Khushi 0 Posted August 1, 2018 Report Share Posted August 1, 2018 Hi In UVM_ML, how to connect the following ports (from SystemC-TLM model to rest of the UVM verification env) - sc_in<int> - sc_out<bool> -sc_port<my_if<T1>> - sc_export<my_if<T1>> Thanks Quote Link to post Share on other sites
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.