Jump to content
Sign in to follow this  
wwen

uvm hdl force and simulator optimization

Recommended Posts

can't seem to be able to use uvm_hdl_force in vcs, unless debug_all is specified. 

is there a tab file or at least maybe some vpi file created underneath that can be used to create a tab file to be passed in to vcs  so uvm_hdl_force can work without using debug all?  

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Sign in to follow this  

×
×
  • Create New...