Jump to content

VCS run option to use random seed?


Recommended Posts

@kurtlin , do you know this by chance?   

I am looking for each VCS simulation 'run' to use a different seed. 

(I'm using EDAPlayground, so don't have access to a set of user guides.)

 

On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below.  (I suspect that -sv=2009 is a superset of "-assert svaext".  So, I'll probably stick with that.  Thanks again.)

Quote

"You must use the –assert svaext compile-time option to enable the new IEEE Std. 1800-2009 compliant SVA features."

 

Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date")

**1: 

 

Link to post
Share on other sites
  • 4 months later...

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...