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  1. Respected Shine2828, I do not quite correspond to the profile you expect from a user on this forum, but will try to answer your question: The run_phase function runs two processes in parallel (in the fork ... join block). One is writing to the ram model when a write transaction is available at the write fifo. The other process is checking (read and verify) the real read data against the data in the ram model when a read transaction is available in the read fifo.
  2. Sorry, it looks like it's available from version 2014.03
  3. Hi Tarun, Thank you for your answer. I cannot find any -F, -P or -T options in the ralgen help menu. When I try to run the cmd: ralgen -T -uvm -l sv -t ral_top -o ral_top ral_top.ralf I am getting: "Error: Unknown option character 'T' specified" I am using version 2013_06 of ralgen. The "ralgen -h" commands does not help me further... Any idea? Thanks Florian
  4. Hi, When using ralfgen to generate uvm register models, the whole model is generated in one big file, include all the submodules. This affect the reusability. I would prefer to reuse model that were generated for submodules instead. As an example, here is a basic hierachical structure of a system: Module A |-Module x with their corresponding ralf file: ModuleA_regmodel.ralf: source Modulex.ralf system ModuleA_regmodel { bytes 4 block Modulex = my_modulex@0X000000 } Modulex_regmodel.ralf: block Modulex_regmodel{ bytes 4 register dummy { bytes 4; } } Running ralfgen will give me the following uvm regmodel in moduleA_regmodel.sv `ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_reg_modulex_regmodel_dummy extends uvm_reg; [...] endclass : ral_reg_modulex_regmodel_dummy class ral_block_modulex_regmodel extends uvm_reg_block; [...] endclass : ral_block_modulex_regmodel class ral_sys_modulea_regmodel extends uvm_reg_block; [...] endclass : ral_sys_modulea_regmodel `endif Now, for reusability, it would be preferrable to have two files instead: modulex_regmodel.sv `ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_reg_modulex_regmodel_dummy extends uvm_reg; [...] endclass : ral_reg_modulex_regmodel_dummy class ral_block_modulex_regmodel extends uvm_reg_block; [...] endclass : ral_block_modulex_regmodel `endif moduleA_regmodel.sv `ifndef RAL_MODULEA_REGMODEL `define RAL_MODULEA_REGMODEL import uvm_pkg::*; class ral_sys_modulea_regmodel extends uvm_reg_block; rand ral_block_modulex_regmodel my_modulex; [...] endclass : ral_sys_modulea_regmodel `endif Now, is there a way to generate moduleA_regmodel as is, without deleting the modulex_regmodel class declaration after each generation? I was thinking of having a modulex_regmodel_empty.ralf: block Modulex_regmodel{ } And source it in ModuleA_regmodel.ralf, but I get an error. Other ideas? Thank you!
  5. Cast cannot allocate for elements that are in my_packet and not in basePacket. In your example, P2 cannot be casted from P1 because the object is not created as a "my packet". To make it work, try (even though the scenario is a bit different): My_Packet P2 = new; BasePacket P1; initial begin P1 = P2; P1.printA; P1.printC; $cast(P2, P1); P2.printA; P2.printC; end cf http://www.edaplayground.com/s/934/1124
  6. Is that what you are looking for? http://forums.accellera.org/topic/742-referencing-an-array-of-uvm-analysis-imp-in-a-scoreboard/?hl=listener#entry2975 Flo
  7. Not quite correct. See http://forums.accellera.org/topic/1097-overriding-uvm-version-obtained-from-vcs-with-a-version-of-uvm-from-accellera/
  8. My guess is that uvm is not installed with this version of VCS, so you can't use -ntbopts. Try to compile the uvm source directly with +incdir ../src
  9. Hi Did you try m_sequencer.set_report_severity_id_verbosity(UVM_INFO, "AXI4STREAM_SLAVE", UVM_LOW) ? Florian
  10. I have a book here that recommends to use logic in interfaces (System Verilog for Verification, Chris Spear / Greg Tumbush, chapter 4.2.8). This is then not valid when using clocking blocks?
  11. Thank you. I don't quite understand though. The signal of my_if interface will always be single-driven, as long as I am not using the master_cb clocking block in my monitor. Is that because the interface is connected at run-time and the compiler won't know about which clocking block will drive/monitor the interface at compile time? It checks for the worst case Could I use modport to avoid this as well? How?
  12. Hi, I have issues connecting my interface to my dut when using the cadence compilator (vcs does not give any warning here): See the source code below. I get the following warning: ncelab: *W,ICDPAVW (<my_file>): Illegal combination of driver and procedural assignment to variable my_data detected (output clockvar found in clocking block at line <n> in file <my_file>). .out_data (my_if.my_data) Any idea what is wrong her? Thank you Here's the source code: interface my_if (input bit clk); logic reset; logic data; clocking master_cb @ (posedge clk); output data; endclocking // cb clocking slave_cb @ (posedge clk); input data; endclocking // cb clocking passive_cb @ (posedge clk); input data; endclocking // cb endinterface : my_if module tb_top; logic clk; logic reset; /* Dut interfaces */ my_if my_if(clk); /* Clocks and reset gen*/ <...> assign my_if.reset = reset; dut my_dut( .clk (my_if.clk), .arst (my_if.reset), .out_data (my_if.data) ); initial begin : ib_main <...> end endmodule
  13. Thank you Logie. In your last suggestion, how would I access my_if outside the generate loop? The dut instantiation is connecting to the different my_if.
  14. Logie, thank you for your comment, it almost worked and gave me a better error (it didn't like non-constant arg from my previous inner for loop). It now compiles by using a generate loop around the uvm_config_db genvar i; for (i=0 ; i < 3 ; i++) begin initial begin string inst_name; $sformat(inst_name, "*.source[%0d].*",i); uvm_config_db#(virtual test_if #(.G_NUM_PAR_CHANNELS(4)))::set(uvm_root::get(), inst_name, "vif", my_if); end end Any ideas about the related issue?
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