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fbochud

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  1. Respected Shine2828, I do not quite correspond to the profile you expect from a user on this forum, but will try to answer your question: The run_phase function runs two processes in parallel (in the fork ... join block). One is writing to the ram model when a write transaction is available at the write fifo. The other process is checking (read and verify) the real read data against the data in the ram model when a read transaction is available in the read fifo.
  2. I have a book here that recommends to use logic in interfaces (System Verilog for Verification, Chris Spear / Greg Tumbush, chapter 4.2.8). This is then not valid when using clocking blocks?
  3. Thank you. I don't quite understand though. The signal of my_if interface will always be single-driven, as long as I am not using the master_cb clocking block in my monitor. Is that because the interface is connected at run-time and the compiler won't know about which clocking block will drive/monitor the interface at compile time? It checks for the worst case Could I use modport to avoid this as well? How?
  4. Hi, I have issues connecting my interface to my dut when using the cadence compilator (vcs does not give any warning here): See the source code below. I get the following warning: ncelab: *W,ICDPAVW (<my_file>): Illegal combination of driver and procedural assignment to variable my_data detected (output clockvar found in clocking block at line <n> in file <my_file>). .out_data (my_if.my_data) Any idea what is wrong her? Thank you Here's the source code: interface my_if (input bit clk); logic reset; logic data; clocking master_cb @ (pose
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