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Changes in generic paylod are not reflected in UVM side

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Hi Guys

I have a scenario where I have an target module in SystemC-TLM2 with a tlm_target_socket.

I developed a UVM based verification env to verify that SystemC-TLM2 model.  In UVM test bench I have an initiator module which calls b_transport with some payload and in SystemC-TLM2 target side I have the implementation of b_transport.

I can see the the payload reaching on systemc side but when I change the payload (e.g. data or address) in b_transport implementation, the changes are not reflected on UVM initiator after the b_transport call returns.

I am not able to understand what is going wrong. Any help or guidance will be highly appreciated,

I am using Cadence UVM-ML for this.



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