accessing register from more than one master

[verifier]

Hi

I have one register model with two different master.

both has the same address map.

do I still need to create separate address map for each master ?

I want to access registers concurrently from both the masters.

I am not sure how to set sequencer for register map in this case and how to run different register sequences in each master sequencer.

can you provide sum suggestions ?

Verifier

[janick]

The register model is not designed to work with two masters on the same bus. You can access the register model from two different threads and they'll all be accessed using the same bus master. Functionally, that amounts to the same thing.

You could model all registers in your block as shared registers and use multiple address maps, but that would not buy you anything functionally.

If you are trying to verify concurrent access from different bus masters, use bus-level transactions: that is a bus-level stimulus, not a register level stimulus.

[verifier]

Hi Janick

Thanks for the reply.

I have different path to access same registers so there are two different buses which can access the same registers.

I was thinking to use all masters to run register sequences concurrently with rtl slaves and memories.

so there is no way to do it using register models.

other way to do is use bus level transactions as you mentioned.

Verifier

[verifier]

also one register model instance can run on only one master in environment.

is my understanding correct ?

[janick]

I have different path to access same registers so there are two different buses which can access the same registers.

Now THAT is different. Each bus has its own master that then correspond to a different address map. The registers are instantiated in the block but added to each map. You need to specify the map to use when accessing the register, although one will be picked by default if you don't.

also one register model instance can run on only one master in environment.

Only one master per physical bus. There can be multiple masters, as long as they are on different buses.

[uwes]

this sounds like http://eda.org/svdb/view.php?id=3369

[verifier]

Janick,

Thanks for clarification.

so if I run inbuilt uvm register sequence it will run on first master's sequencer with first map and then it will run on second master's sequencer with second map.

is there anyway to filter testing of registers with map like it is done for register and reg blocks using NO_REG_TEST ?

Verifier

[janick]

Depends on the test, but essentially yes.

Not in the built-in sequences. There are so may ways one can access/test registers, there is no way the TSC can provide pre-defined tests that will satisfy everyone.

Now's the time to take advantage of the open source nature of UVM!

[Murali_A]

Hi  All,

Requirement : UVM RAL implementation: 2 Masters are trying access same register of single register Block/ uvm_register Map.

 

Hi  All,

I have similar requirement where we have 2(two) master agents are trying to access/program the same register in single Register Block.

1) Master_1 --> Write's 'h444 to Reg_0 present in Regblock_A 

2) Master_2 --> Reads Reg_0 should get the Read data 'h444 (which is our earlier write).

Can you please share your inputs on how to implement this in my ENV? Any reference docs, links are appreciated. 

 

 

[David Black]

You could setup the masters to access through a common agent and use the lock/unlock methods in the sequence. This something I teach in Doulos UVM Adopter course.

 

[Murali_A]

Hi David Black,

Thankyou for your response, I have good knowledge on basic UVM RAL and my requirement is about RAL implementation especially "accessing register from more than one master". From your response i got to know that is being covered as part of  Doulos UVM Adopter course. Can you please share the course and Price details , i tried sending a enquiry form to doulous from  link " https://www2.doulos.com/forms/enquiry " but it didn't work for some reason.