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Writing to a register when the status is UVM_NOT_OK

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In UVM_REG, what is the intended behavior when a write to a register triggers a bus error? I would expect that the mirrored value is not updated as long as I signal the bus error inside the bus2reg method of my reg_adapter. Here is a slightly modified excerpt from the user guide.

virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
  apb_rw apb;
  if (!$cast(apb,bus_item)) begin
    `uvm_fatal("NOT_APB_TYPE", "Provided bus_item is not of the correct type")
  rw.kind = apb.kind ? UVM_READ : UVM_WRITE;
  rw.addr = apb.addr;
  rw.data = apb.data;
  rw.status = apb.error ? UVM_NOT_OK : UVM_IS_OK;

I see that even in cases when the APB bus signals an error and I set the status in the rw as UVM_NOT_OK, the mirrored and the desired values of my registers get updated. Am I interpreting this UVM_NOT_OK thing wrong?

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  • 7 months later...

Hi Tudor,


the same problem i am also facing.


i just want to check if status is UVM_NOT OK, then RAL model is updating or not.


then i hardcoded the status in bus2reg wantedly and i used explicit predictor method (FRONT DOOR),


when i read status register from DUT then in seq, i am getting read data as 0. but at the same time when i did "get" for the status register in RAL, then my value is already updated.


how to control ral updation when status is UVM_NOT_OK. ?

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  • 6 years later...
On 2/16/2015 at 8:32 AM, tudor.timi said:

What I ended up doing was creating my own subclass of uvm_reg_predictor that handles UVM_NOT_OK. I don't have access to the code right now, but it should be pretty easy for you to do by just having a quick look at that class.

Updating predictor sounds a good idea . Did you keep the adapter code as you mentioned or changed it back to standard 

     rw.Data = apb_trans.Data;
       rw.status = UVM_IS_OK;

  end else begin  
       rw.status = UVM_NOT_OK;



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