Valid HDL path using DPI/VPI to access std_ulogic_vectors?

[johannes.walter]

Hey!

The last couple of days I am trying to get the UVM backdoor for my register model working. I have my DUT's register file written in VHDL utilizing many std_ulogic_vectors as registers.

Now I would like to set a HDL path to access these std_ulogic_vectors via the DPI/VPI mechanisms of UVM. For example one of the std_ulogic_vector registers has the path "top.dut.sfr_adc_conf_reg_s".

I experienced many different behaviours while trying to get this working.

1. With registers that have only 1 bit and are mapped to a std_ulogic everything is working. "sfr_adc_conf_reg_s" is std_ulogic:

adc_conf_reg.add_hdl_path('{ '{"sfr_adc_conf_reg_s", -1, -1} });

2. With bigger registers which are mapped to std_ulogic_vectors it is not working.

"sfr_adc_conf_reg_s" is std_ulogic_vector(15 downto 0):

adc_conf_reg.add_hdl_path('{ '{"sfr_adc_conf_reg_s", -1, -1} });

Result is a segmentation vault in QuestaSim:

# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 1531 ns  Iteration: 0  Process: /uvm_pkg::uvm_sequence_base::start/#FORK#299_2a96e47e7 File: /home/walterjo/uvm-1.1/src/dpi/uvm_hdl.svh
# Fatal error in Module uvm_pkg at /home/walterjo/uvm-1.1/src/dpi/uvm_hdl.svh line 121

3. When I add a range to the HDL path the C function in uvm_hdl.c tries to access each bit independently. The segmentation fault disappears but then QuestaSim cannot find the according VHDL signal.

"sfr_adc_conf_reg_s" is std_ulogic_vector(15 downto 0):

adc_conf_reg.add_hdl_path('{ '{"sfr_adc_conf_reg_s[15:0]", -1, -1} });

Result in QuestaSim:

# UVM_ERROR: get: unable to locate hdl path top.dut.sfr_adc_conf_reg_s[0]
#  Either the name is incorrect, or you may not have PLI/ACC visibility to that name

In my uvm_env I set the HDL root path to "top.dut" and I also added +acc=rnb to the vcom and vlog parameters.

Has anyone an idea how to set the HDL path correctly to get access to the VHDL vector registers?

Any help would be appreciated!

Regards,

Johannes

[adielkhan]

hi,

UVM currently does not (yet) support mulitple languages like VHDL it is SystemVerilog only, as is DPI.

To achieve what you want you will need to go via SystemVerilog to access the VHDL signals.

You could wrap it in SV or use SVA bind statements to connect the SV & VHDL.

If you feel it is a high prioirty to have UVM directly access VHDL without SV-wrapper then please add it to the requirements spreadsheet.

-adiel

[johannes.walter]

Hi,

thank you for your reply. I didn't know that this is not working with VHDL.

What I did now for the time being is to mirror the VHDL signals to a SystemVerilog module using QuestaSim's Signal Spy. When I change the HDL path to this module DPI/VPI is working fine.

We are also thinking about adding some Mentor FLI functionality to uvm_hdl.c - although this will only work with QuestaSim.

Regards,

Johannes

[johannes.walter]

Okay. Sorry. Signal Spy doesn't do the trick. At first I was just reading from the registers but now as I want to write Signal Spy is not the appropriate solution. I will try the SVA bind statements ...

Thanks

Johannes

[uwes]

hi,

another solution instead of dpi/vhpi/pli/.... is to use a custom backdoor and simply reference the registers via an out-of-module-reference.

/uwe

[johannes.walter]

Hi!

I tried all the suggested solutions. Implementing a custom backdoor worked best for me. This way its possible to use UVM combined with VHDL without problems and without modifying any uvm_dpi C functions.

Here is my code for QuestaSim:

class my_reg_backdoor extends uvm_reg_backdoor;
     virtual function void read_func(uvm_reg_item rw);
          rw.value[0] = $root.top.dut.my_reg;
          rw.status = UVM_IS_OK;
     endfunction
     
     virtual task write(uvm_reg_item rw);
          string data;
          data.bintoa(rw.value[0]);
          $sformat(data, "%012d", data); // bit width = 12
          $signal_force("/top/dut/my_reg", data, 0, 1);
     endtask
endclass

Thank you all!

Uwe, you just made my day!

Regards,

Johannes

[Radhika Jain]

@johannes.walter; is my_reg defined in uvm_reg_backdoor? how do I provide the reg name to this function?