paul Posted June 21, 2011 Report Share Posted June 21, 2011 hello, I have a register model describing register with various size 16bits, 32 bits or 128 bits. In my uvm_reg_block this registers are well defined but when I tried to access the 128 bits register the data width of the transaction is only 32 bits instead of 128. Futhermore, this issue happened only if the address of my 128 bits register is higher than my 32 bits register. Would anyone have a rational explanation Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.