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get after write doesn't update desired value, mirror gets updated correctly on read

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I see that the write is happening correctly in the RTL, but the get called after write doesn't returns "0" instead of the write value.

the mirror(since explicit prediction) called after read returns the correct value that was written in. 

reg_model.amp_reg.ampstate_8_reg_blk.svm_control_reg.write(.status(status),.value(in_data0), .extension(ext),.parent(this));

ctrl_value = reg_model.amp_reg.reg_blk.control_reg.get();

reg_model.amp_reg.amp_reg.reg_blk.control_reg.read(.status(status), .value(read_data),.extension(ext),.parent(this));

value = reg_model.amp_reg.reg_blk.control_reg.get_mirrored_value();
          `uvm_info("reg_seq", $sformatf("The mirror value is:%0h",value), UVM_HIGH)

        if(ctrl_value == value)   
              `uvm_info("reg_seq", "svm_control_reg read back value matches write ", UVM_LOW)


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