Jump to content

Search the Community

Showing results for tags 'uvm-ieee'.

  • Search By Tags

    Type tags separated by commas.

  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End

Last Updated

  • Start

    End

Filter by number of...

Joined

  • Start

    End

Group

AIM

MSN

Website URL

ICQ

Yahoo

Jabber

Skype

Location

Interests

Biography

Location

Interests

Occupation

Company

Found 2 results

  1. ysimhony
    Hi, I am trying to port my uvm code from UVM 1.1d to UVM-IEEE. Having the following line in my code: `uvm_field_queue_object(p_ext_agents, UVM_ALL_ON | UVM_REFERENCE) where uvm_component p_ext_agents[$]; cause the following compile error: `uvm_field_queue_object(p_ext_agents, UVM_ALL_ON | UVM_REFERENCE) | xmvlog: *E,DBITNS (sia/lib/sv/cdn_iwb/sv/cdn_iwb_routing_model.sv,172|98): The argument of the system function call was not of bit-st
  2. sharvil111
    === Posted same query over here, but unfortunately got no response so far. Henceforth trying it out in latest forum === When jumping form run phase to extract phase, the UVM BCL somehow invokes the extract phase twice. But when jumping from run phase to final phase, the final phase is invoked once only. Here I am using uvm_domain to jump from one phase to another. In the following pseudo code, the jump does not happen for extract phase. Moreover the extract phase display is coming twice. While the jump happens gracefully when jumping to final phase. package pkg; import uvm_pkg:
×
×
  • Create New...