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Showing results for tags 'sequencer'.
In my testbench I have two background sequences (call them S1 and S2) perform register access and a test that has multiple threads ( call them T1 to T7) also performing register access on the same shared bus. T1 through T7 need to lock the sequencer in order to perform multi-cycle transactions on the CPU bus. The scenario is S1 issues a write, resulting in arb_sequence_q.size == 1 and arb_sequence_q.request == SEQ_TYPE_REQ in the same simulation tick, T1 through T7 issue lock requests. arb_sequence_q.size() == 8 and arb_sequence_q is still the S1 request S2 issues a re