how to pass a cmdline argument file when run simulation

[xndwds313]

As I know, we can use clp(command line processor) interface to specify the run time options such as case name, verbosity, configurations in the command line when run simulation. when there is a case that I have too many run time arguments that I want to put them in to a file so that I can modify that file to run case with different arguments. How can I do this with UVM? I know for VMM we can use a run time option call -vmm_opts_file filename to do this, not sure we can do this in UVM to specify a run time argument file.

[adielkhan]

Hi,

The CLP leverages VPI routines. Therefore, it depends on how your simulator accepts commandline args.

I believe the big-3 all support -f switch for runtime files as this is what is used in the UVM regression-suite.

For instance with VCS you would do

./simv -f run.args

thanks,

adiel

[xndwds313]

Hi,

what you mentioned is the compile option not the runtime option(-f / -F), I have tried this and it does not work.

Thanks,

Daswang.

[adielkhan]

Hi,

./simv is the runtime command.

As stated, we use this in the UVM regression suite.

thanks,

adiel.

[xndwds313]

Ok, can you provide more details about how to do this?

I just compile a simple sv file and I can run it with command "./simv -l vcs.log" then I put "-l vcs.log" into run.args file, then when I run command "./simv -f run.args", no vcs.log file generated.

[Roman]

Hi,

what you mentioned is the compile option not the runtime option(-f / -F), I have tried this and it does not work.

Thanks,

Daswang.

Hi,

I am using cadence irun simulator , "irun" is also a runtime command.

So why not put all your run time arguments into args.f and then use "irun -f args.f"

BTW, you also need do "get_**" (uvm_cmdline method) to return a queue and fetch the options from command line , do the specific things in your TB.

[xndwds313]

what we do is that we use vcs to compile our code to generate a simv file which is executable, then we use command "./simv +UVM_TEST=....." to run the case, and we do not need to use vcs to compile the code again when we use different runtime arguments specified in the command line. for example we compile our code and then we get the simv file, we use the command line below to run two cases with different configutaions, but we do not find a way to put the runtime options into a file then we use the file as a argument just like vcs compile option -f which is used to specify the compile time options.

"./simv +UMV_TEST=my_test ++uvm_set_config_int=uvm_test_top.u_ilaken_cfg,ilaken_mode,0"

"./simv +UMV_TEST=my_test ++uvm_set_config_int=uvm_test_top.u_ilaken_cfg,ilaken_mode,1"

[adielkhan]

Hi,

You can place your UVM plusargs in a file and this is tested to work with 3-major simulators.

i.e

vcs -sverilog -ntb_opts uvm test.sv

./simv -f uvm_args.f

uvm_args.f:

+UVM_TESTNAME=test

test.sv:

program top;

import uvm_pkg::*;
`include "uvm_macros.svh"

class test extends uvm_test;
  `uvm_component_utils(test)

  function new(string name, uvm_component parent = null);
     super.new(name, parent);
  endfunction

  virtual task run_phase(uvm_phase phase);
     `uvm_info("MSG1", " message ", UVM_LOW)
  endtask
endclass
initial run_test();

endprogram

thanks

adiel.

[xndwds313]

Thanks a lot for all you guys, I have successfully to specify the uvm arguments in a file, we must not add any other arguments in that file, or the arguments will not work properly, for example when I add -l vcs.log in the argument file, then the simulator can not extract the runtime arguments correctly.

[Shaikh Abuzar]

For VCS tool, how to run the regression? Is there any command to run the regression?
Can we pass a file to simv, which contains multiple testcases as below
+UVM_TEST_NAME=test1

+UVM_TEST_NAME=test2

+UVM_TEST_NAME=test3

will it run all the cases one by one?

[David Black]

UVM is specifically structured to require running one test at a time. You can write a simple script (e.g., bash, python or tcl) to invoke any of the simulators multiple times with different UVM_TEST_NAME's.

 

 

[Bas Arts]

EDA vendors typically also provide tooling on top of simulators, to orchestrate/analyse/debug/optimize large test sets.