How to do two bus2reg operations for a single transaction

[mon]

I have started to learn the UVM and when I imagine how to use it for a simple components from our projects it seems that there is a lot of issues I will need to resolve. Mainly in case of I would like to use the register layer.

1) I have a communication protocol with both read and write operations in the same frame and I am not sure how to implement the register adapter in case of I would like to have both the request and response in the same transaction. I can implement the reg2bus method, but don't sure how to do two bus2reg operations for each transaction. Is there some recommendation or do I need to sent each transaction twice with an additional read / write flag to distinguish them in adapter?

• REQ: <status_addr>, <control_addr>, <control_data>
• RSP: <flags>, <status_data>

2) What is the recommended way to "discard" a transaction from monitor to reg. predictor in case of I have some non-register related operation/command (e.g. test mode entrance, programming, wake-up request,..)? Should I use the UVM_NOT_OK status in bus2reg method or do I need to create a dedicated port and do some filtering between the monitor and predictor?

 

Thank you.

[David Black]

There are several ways to do this:

1. Use the register front door sequence
2. Create a layered agent with a high-level driver/transaction that directs the low level driver to perform two transactions to accomplish the desired goal

[mon]

Hi David,

thank you for the response. As I wrote, the path from the register model to driver is not so big issue. A layered agent or splitting of the transaction would definitely resolve the issue, but it seems to me as too complex if I need it only for purpose of register model. Basically the transaction contains all necessary information.

I just looked into the source code of predictor and I have two ideas:

1. I can create two instances of umv_register_predictor -  the first for the read operation and the second for the write operation. Both of them connected to the same analysis port. I didn't check if I can do that with the same map, but seems to me as a very simply solution.
2. In case of the first solution would not be possible, I can extend the uvm_register_predictor class to call the write method twice each time when a transaction is received.

In both cases, I only need to add a r/w flag into the adapter to be bus2reg method aware of what kind of operation is converted.