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  1. Hi, Could anyone please clarify what's the difference between run_phase and main_phase in uvm_component? What are both do for? Thanks, Brian
  2. Hi Philipp, Thanks for your explanation. So you mean the simulator should not issue the warning because sc_pending_activity_at_current_time() returns true, which is caused by 'clk.write(1)' ----- no runnable process but has update-request ? Best Regards, Brian
  3. Hi, I'm trying to co-simulate verilog and systemc using vpi. The basic step is At verilog side, whenever posedge of clock occurs, call sc_start(delta) to let systemc time catch up verilog time; Execute clk.write(1) Call sc_start(0) to let the write really occur at systemc side (clk posedge ocurrs at evaluation phase of systemc side ) Then call another sc_start(0) to let the updated systemc output to be propagated to verilog side. Actually, I merge step3 and step4 to the following while(sc_pending_activity_at_current_time()) sc_start(0); All works fine except the warning which fired at step 3: Warning: (W571) no activity or clock movement for sc_start() invocation In file: ../../../../src/sysc/kernel/sc_simcontext.cpp:1606 Here my question is that, At what condition, sc_pending_activity_at_current_time() will return true? Will executing clk.write(1) let it to return true? I suppose yes. What's the popurse for this warning? It seems this warning will not be fired at systemc-2.2.0, but only systemc-2.3.0 Thanks in advance, Brian
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