The difference between run_phase and main_phase in uvm_component

[brxue]

Hi,

 

Could anyone please clarify what's the difference between run_phase and main_phase in uvm_component? What are both do for?

 

Thanks,

Brian

[sathyakiran.p]

sequence will start execution in main_phase , where as, driver will start execution in run_phase. Both are concurrent phases.

 

 

Thanks,

Satya

[David Black]

Actually, you can start a sequence in any phase. It is more important to understand the domain/scheduling relationships between the task based (i.e. runtime) phases. UVM undergoes a number of pre-simulation phases (build, connect, end_of_elaboration, start_of_simulation) that are all implemented with functions. Once those are completed, the task based phases begin. The standard includes two schedules. One is simply the run_phase, which starts executing at time zero and continues until all components have dropped their objections within the run_phase. The other schedule contains twelve phases that execute parallel to the run phase. They are: pre_reset, reset, post_reset, pre_config, config, post_config, pre_main, main, post_main, pre_shutdown, shutdown, and post_shutdown. They execute in sequence. Every component has the opportunity to define or not define tasks to execute these phases. A phase starts only when all components in the previous phase have dropped their objections. A phase continues to execute until all components have dropped their objections in the current phase.

 

Many companies use the run_phase for everything because there are some interesting issues to consider when crossing phase boundaries. In some respects it may be easier to use uvm_barriers for synchronization. Drivers and monitors (things that touch the hardware) are usally run exclusively in the run_phase, but there is nothing to prevent them also having reset_phase, main_phase, etc...

[brxue]

Hi David, thanks for your elaboration.

[sathyakiran.p]

Hi David,

 

when we define run_phase and other phases(main_phase, reset_phase...) in a component. It will override all other phase, but, execute only run_phase??

 

Please correct me I am wrong.

 

Thanks,

Satya

[dave_59]

No, it will not override other phases. The run_phase will be in parallel with the other series of phases.

[sathyakiran.p]

Thanks dave for clarification.

[Hari krishna]

Hi,

Run phase executes parallel but inside run phase executes sequencial order HOW?

 

Thanks,
Hari

[David Black]

Standard UVM executes under SystemVerilog, and the answer to your question lies partly within how SystemVerilog simulators work.

Consider the following example on EDAplayground: https://edaplayground.com/x/aSPG.