brxue Posted April 23, 2014 Report Share Posted April 23, 2014 Hi, Could anyone please clarify what's the difference between run_phase and main_phase in uvm_component? What are both do for? Thanks, Brian Quote Link to comment Share on other sites More sharing options...
sathyakiran.p Posted April 23, 2014 Report Share Posted April 23, 2014 sequence will start execution in main_phase , where as, driver will start execution in run_phase. Both are concurrent phases. Thanks, Satya Quote Link to comment Share on other sites More sharing options...
David Black Posted April 23, 2014 Report Share Posted April 23, 2014 Actually, you can start a sequence in any phase. It is more important to understand the domain/scheduling relationships between the task based (i.e. runtime) phases. UVM undergoes a number of pre-simulation phases (build, connect, end_of_elaboration, start_of_simulation) that are all implemented with functions. Once those are completed, the task based phases begin. The standard includes two schedules. One is simply the run_phase, which starts executing at time zero and continues until all components have dropped their objections within the run_phase. The other schedule contains twelve phases that execute parallel to the run phase. They are: pre_reset, reset, post_reset, pre_config, config, post_config, pre_main, main, post_main, pre_shutdown, shutdown, and post_shutdown. They execute in sequence. Every component has the opportunity to define or not define tasks to execute these phases. A phase starts only when all components in the previous phase have dropped their objections. A phase continues to execute until all components have dropped their objections in the current phase. Many companies use the run_phase for everything because there are some interesting issues to consider when crossing phase boundaries. In some respects it may be easier to use uvm_barriers for synchronization. Drivers and monitors (things that touch the hardware) are usally run exclusively in the run_phase, but there is nothing to prevent them also having reset_phase, main_phase, etc... aalpa23, acc_sysC, asicengineer and 3 others 6 Quote Link to comment Share on other sites More sharing options...
brxue Posted April 24, 2014 Author Report Share Posted April 24, 2014 Hi David, thanks for your elaboration. Quote Link to comment Share on other sites More sharing options...
sathyakiran.p Posted April 24, 2014 Report Share Posted April 24, 2014 Hi David, when we define run_phase and other phases(main_phase, reset_phase...) in a component. It will override all other phase, but, execute only run_phase?? Please correct me I am wrong. Thanks, Satya Quote Link to comment Share on other sites More sharing options...
dave_59 Posted April 24, 2014 Report Share Posted April 24, 2014 No, it will not override other phases. The run_phase will be in parallel with the other series of phases. Quote Link to comment Share on other sites More sharing options...
sathyakiran.p Posted April 24, 2014 Report Share Posted April 24, 2014 Thanks dave for clarification. Quote Link to comment Share on other sites More sharing options...
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