problem with uvm ral read/mirror

[assafgedalia]

Hi,

 

I am having some trouble with creating a register model for my DUT.

It is intended for APB transactions.

I included an adapter and a predictor.

When i try to read or mirror a register i have written to i get a wrong value.

when looking at the waves i see that ALL my transactions are done properly - read and write.

also i noticed that the bus2reg function is called twice for each transaction, and in the write transactions both

calls to bus2reg function gives the same values but in the read transaction, the first call to bus2reg is good

and in the second call i get 0 in the data.

 

Any thoughts would be much appreciated...

 

my adapter:

 

    virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);

        apb_transaction tr;

        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH);        

        

        if (!$cast(tr, bus_item)) begin

            `uvm_fatal("REGERR", "%m: Failed to convert bus2reg");

        end

        rw.addr     = tr.addr;

        rw.data     = tr.data;

        rw.kind     = tr.op_kind;

        rw.status   = UVM_IS_OK;

 

        `uvm_info("DEBUG", $sformatf("%m. *** rw.addr = %0d, rw.data = %0d, rw.kind = %s, rw.status = %s", rw.addr, rw.data, rw.kind.name, rw.status.name), UVM_HIGH);

    endfunction: bus2reg

 

Thx,

Assaf

[tudor.timi]

Is your adapter configured with the provides_responses switch? That would explain why you get bus2reg called twice. One call would be from the sequencer-driver-sequencer path and the other would be from the monitor. If this is the case, it might be that you aren't updating the response item for reads inside the driver with the appropriate data, which would explain why you get 0.

[assafgedalia]

Tudor,

 

there is no place in my monitor code where i call bus2reg, is it done implicitly somewhere?

if this is indeed the case, and if i understand you correctly, one of these bus2reg calls is done incorrectly?

so how exactly do i fix this issue? what exactly do you mean by "updating the response item for reads inside the driver with the appropriate data" ?

i tried to look up some examples for the sequencer-driver communication and all the examples i see look something like this:

 

            seq_item_port.get_next_item(req);

            rsp = apb_transaction::type_id::create("rsp", this);

            rsp.set_id_info(req);

 

            // Flag item done

            seq_item_port.item_done();

 

            seq_item_port.put_response(rsp);

 

i tried to add this code to my driver but it did not solve my problem.

 

more help would be much appreciated

 

Thx,

Assaf

[assafgedalia]

I Understand now what you meant, i fixed the driver to handle the read correctly and it solved the problem.

 

Thanks.

[Lohith]

Hi May i know how you fixed the issue. I am also facing a same issue.

I am trying to read the default values of the registers. I see correct values on the waves but still i see mismatch msg in the logs.

 

Thanks in advance

[Ai_Ar]

I am facing the same issue. I have an explicit predictor connected to the monitor analysis port, provide_respons is set to 0 in the adapter. 

So why does predicter invoke bus2reg again if the monitor write already invoked it? the second time data is incorrect.

[pb_reg_adapter] bus2reg: the addr is:fe7c, wr_rd_en is:0 and the data is:1

[REG_PREDICT] Observed READ transaction to register i2c_reg_model.i2c_enable: value='h1

[pb_reg_adapter] bus2reg: the addr is:fe7c, wr_rd_en is:0 and the data is:0
 

[Amy98]

On 5/13/2021 at 4:22 PM, Ai_Ar said:

I am facing the same issue. I have an explicit predictor connected to the monitor analysis port, provide_respons is set to 0 in the adapter. 

So why does predicter invoke bus2reg again if the monitor write already invoked it? the second time data is incorrect.

[pb_reg_adapter] bus2reg: the addr is:fe7c, wr_rd_en is:0 and the data is:1

[REG_PREDICT] Observed READ transaction to register i2c_reg_model.i2c_enable: value='h1

[pb_reg_adapter] bus2reg: the addr is:fe7c, wr_rd_en is:0 and the data is:0
 

In my case bus2reg doesn't even gets called. Any help why this may be issue.