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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. UVM Documentation Issue - UVM_NODEFPRINT Flag

    By cliffc,
    • 3 replies
    • 1.4k views

  2. Grabbing single sequencer by multiple sequences

    By ashutosh,
    • 1 reply
    • 1.4k views

  3. error injection

    By drianf0,
    • 1 reply
    • 2.7k views

  4. Doubt-UVM Agents

    By shine2828,
    • 2 replies
    • 1.5k views

  5. uvm_config_db::set for the same field more than once from a single component

    By eyalbaram,
    • 1 reply
    • 3.9k views

  6. Register modeling for a processor based design architecture using UVM RAL

    By pradeey,
    • 3 replies
    • 1.8k views

  7. Configuration visibility from virtual interface

    By mwhite_cp,
    • 4 replies
    • 2.2k views

  8. Running multiple sequences on the same sequencer in parallel

    By ajustesen,
    • 2 replies
    • 14.2k views

  9. does someone knows the how to bind sequence to sequence ?

    By qiushulin,
    • 2 replies
    • 1.3k views

  10. [uvm_rgm]The issue of reading register in backdoor manner

    By loveuvm,
    • 0 replies
    • 1.5k views

  11. OVM to UVM conversion

    By omahesh,
    • 1 reply
    • 2k views

  12. UVM reg coverage question

    By mwhite_cp,
    • 7 replies
    • 5k views

  13. OVM to UVM conversion

    By suleesh,
    • 3 replies
    • 2.2k views

  14. Parameterized UVC ?

    By uvm_rookie,
    • 5 replies
    • 3.9k views

  15. passing unpacked array to TLM FIFO

    By yeewang,
    • 2 replies
    • 3.4k views

  16. using packer.unpack_object(x)

    By cat,
    • 1 reply
    • 970 views

  17. can we pass `define inside `uvm_do_with ?

    By raghavendrap,
    • 2 replies
    • 2k views

  18. [UVM REG] The issue of backdoor read immediately after write(frontdoor)

    By Roman,
    • 2 replies
    • 2.4k views

  19. Virtual sequencer error

    By qwerty,
    • 1 reply
    • 2.5k views

  20. Registers - Losing bus error status when auto_predict is on

    By achandra,
    • 1 reply
    • 1.6k views

  21. Abstract Classes and the UVM Factory

    By mea1201,
    • 1 reply
    • 3.4k views

  22. OVL and UVM with Systemverilog

    By ejessen,
    • 3 replies
    • 2.1k views

  23. sending register sequences from virtual sequence

    By verifier,
    • 3 replies
    • 1.8k views

  24. Reset Field's Mirrored Value Only

    By bhunter1972,
    • 3 replies
    • 2k views

  25. wait statement in Sequence

    By enchanter,
    • 2 replies
    • 3.3k views
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