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  1. Hello, The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A. interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule Let's assume module A is a master of some Stream interface (like AXI4-Stream),
  2. Hello, I have a library with the sequence which exploits `uvm_info to print messages. It uses UVM_MEDIUM verbosity and AXI4STREAM_SLAVE id. I would like to disable those messages, however I can't change code of the library. For this reason, I have tried to call m_sequencer.set_report_severity_id_verbosity(UVM_INFO, "AXI4STREAM_SLAVE", UVM_HIGH). Please notice, the function is called for sequencer on which the sequence is spawned. The report configuration of the sequencer: # report handler state dump # # # +-----------------+ # | Verbosities | # +-----------------+ # # max verbosit
  3. Hello, I don't know, what is an official way to report a bug. I was not able to add one on the webpage: http://www.eda.org/svdb/view_all_bug_page.php because of lack of an access (I haven't sported any registration form). Anyway, I think that the description of the `uvm_do macro is misleading. It states: "This macro takes as an argument a uvm_sequence_item variable or object. The argument is created using `uvm_create if necessary, then randomized". Actually `uvm_create is called every time, no matter whether SEQ_OR_ITEM is null or not. My preliminary impression was that passing a non-'null'
  4. Hello, I would like to ask whether the reference design exits which would introduce an error injection and would present a methodology how to handle it. I am acquainted with the basic examples like the UBUS, APB and UVM_ref_flow_1.1 (Cadence's contribution). However, all of them, I understand for simplicity, work on transaction level, where a driver sends a content of a sequence_item in the proper way. In my case, I would like to add the error injection on low level. For example, in case of a SERDES, it could be a simple introduction of disparity errors, wrong codding, ect. Is any design pat
  5. Hello, Is it safe ? I mean, I use the same trick. However, I am wondering, whether it is fine, that somewhere else in the top module I have: initial run_test("My_Test") Does it not introduce a race hazard of initial processes ? Of course, one could put start of the test as a condition in the last iteration of the generate loop, but in my opinion is not a clean solution...
  6. Hello, Is it safe ? I mean, I use the same trick. However, I am wondering, whether it is fine, that somewhere else in top I have: initial
  7. Dear Erling, Thanks a lot for your reply. The issue has been reported to Mentor Graphics. They confirmed it is a bug ( Defect DVT-31448 ). Your idea of possible workaround of course works. Adrian
  8. Hello, I would like to write a generic virtual sequence, which will spawn another sequences. Since I would like to to keep it generic, the type of spawned sequences should be defined by the overriding facility of the factory. My problem is that the code: class vir_seq extends uvm_sequencer#(); ... virtual task pre_body(); uvm_sequence_base seq; seq = uvm_sequence_base::type_id::create("my_name"); endtask; ... instead of creating the overriding type (let's say my_seq), creates vir_seq. One comment: I use the uvm_sequence_base instead of the uvm_sequence#(T) because I don't want to have
  9. Hello, The uvm_queue and uvm_pool don't have implemented do_compare function. Could somebody please explain me why ? Maybe that feature could be added in future releases. I think that even `uvm_field_queue_object macro would solve the issue... I understand that one can derive from those classes and implement the do_compare by himself. However, I think it would be more convenient to have it already implemented by the standard. Thanks in advance.
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