pradeey Posted September 3, 2012 Report Share Posted September 3, 2012 Hi, I would like to have a test bench architecture wherein the register RAL sequence would trigger the configuration reads and writes to the processor within the design. My approach is that the RAL sequence triggers the sequencer set through set_sequencer call of register map. After the uvm_reg_adapter converts into a sequence item & the sequencer drives it to driver, we placed an API call through which the driver puts SV signature, address & write data into the C memory model. We later wrote a small ASM code which triggers the processor to fetch the address and write data from C memory model locations once it sees the SV signature. Once write is completed, ASM code will overwrite SV signature with ASM signatures which triggers back the SV enviroment to proceed with the next register transaction. (in short, I used a mailbox sort of mechanism after the transaction is triggered by RAL sequence) The disadvantage with this approach is that the no of cycles processor takes to complete one write or read is high as it has to continuously monitor the signature, later fetching the address and write data and only later it will perform the write - which means it took a relatively large no of cycles.. Is there any smarter or efficient way of handling these type of design architectures?? Please suggest. Eagerly waiting for a response. Thanks in advance. Cheers, Pradeep The disadvantage with this approach Quote Link to comment Share on other sites More sharing options...
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