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wait statement in Sequence

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In my case (no uvm_reg),I have to pull a status register from DUT and do the next action base on the respond.

My sequence body task:

virtual task body();

do begin

wait(wait_time); // initial is 1us, defined in new function.

`uvm_do_with(req, {access_kind == READ; len == 1; addr == (cfpga_status_reg/2); })


wait_time = wait_time * 2;

end while ((rsp.dio[0] & 'h00ff) < 'h00FF);

endtask : body

From my simulation, the rsp.dio[0] =0x009f, and it keep pulling the DUT register without wait for WAIT_TIME. And then the simulation stopped after several pullings (no time in my environment).

I don't know why it doesn't wait. And anyone have better solution for this case?


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Because that is not the right syntax to wait for a delay. The wait statement in Verilog waits for the expression to become true, or in your case, non-zero which is always is.

The correct syntax is #(wait_time). Because of timescale issues in Verilog, you should write this as #(wait_time * 1us), where wait_time is the delay in µs.

Also, it is not a good practice to put delays in sequences. Delays are physical properties of an interface and should be handled in the driver.

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If you want to do what you want to do (wait some amount of time based on your read response), then you can define a task in a configuration object that would call a task in the interface to wait a specified amount of time or cycles (assuming that the configuration object would also have the virtual interface handle). Your sequence can then get the configuration object handle via the sequencer, and call the wait task in the configuration object, which will in turn call the wait task in the interface at the physical level. This approach is actually well covered in Mentor's Verification Academy UVM Cookbook.

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