[uvm_rgm]The issue of reading register in backdoor manner

[loveuvm]

Hi, I have some problems in reading registers in backdoor way. There are some registers i want to read in backdoor , registers are as belows,but it seems that only the EVEN order register (C_FPGA_VER_REG_ADR

,C_ADDR_TEST_REG_ADR,C_FPGA_DATE_REG_ADR,...) are read in backdoor !

//////////////////////////////////////////////////////////////////////////

C_TEST_REG_ADR

C_FPGA_VER_REG_ADR

C_TEST_MODE_REG_ADR

C_ADDR_TEST_REG_ADR

C_FPGA_YEAR_REG_ADR

C_FPGA_DATE_REG_ADR

C_RU_LOOP_TEST_REG_ADR

C_CONFIG_9516_REG_ADR

C_PDB_9516_REG_ADR

C_RESET_9516_REG_ADR

C_9516_SYNC_ADR

C_REF9516_SEL_REG_ADR

C_MON_9516_REG_ADR

C_STATUS_9516_REG_ADR

C_RX_PN_TEST_EN_REG_ADR

C_RX_PN_TEST_SEND_CELL_SEL_REG_ADR

C_RX_PARITY_ENABLE_REG_ADR

C_CSM0_TX_VERIFY_ENABLE_REG_ADR

C_CSM1_TX_VERIFY_ENABLE_REG_ADR

C_SERDES_DATA_ENABLE_REG_ADR

////////////////////////////////////////////////////////////////

my code is like this:

class backdoor_seq extends uvm_rgm_sequence;

uvm_rgm_read_all_reg_seq rd_all_seq;

virtual task body();

uvm_rgm_container tmp_cnt = get_container();

...

...

set_config_int("*", "uvm_rgm_read_all_reg_seq.hdl_connection", BACKDOOR);

`uvm_do(rd_all_seq)

...

...

endtask

//////////////////////////////////////

the log file is as attached.

Can anyone help me? thanks!

[ATTACH]41[/ATTACH]

Edited August 30, 2012 by loveuvm
integrity