can we pass `define inside `uvm_do_with ?

[raghavendrap]

Hello all,

I am trying to pass a define value inside the `uvm_do_with like below.

`uvm_do_with(req,{req.addr ==`BLOCK_ADDR ;})

I am seeing below error:

Error-[sE] Syntax error

Following verilog source has syntax error :

"../env/xx_seq_lib.sv", 146 (expanding macro): token is '''

`uvm_do_with(req,{req.addr == `BLOCK_ADDR;})

Please let me know how can i pass the define value.

Thank you

Raghavendra

[mea1201]

This code works perfectly fine for Questa and VCS (don't have access to NC). Only thing that I can guess about it is maybe it's something to do with SV 2009 vs. SV 2005, and whether your simulator supports 2009 or not. `uvm_do_with expands to `uvm_do_on_pri_with, which will expand and substitute in the constraint block containing `BLOCK_ADDR. Maybe this extra level of expansion is a limitation with 2005, but not for 2009. I don't know; I'm really guessing on this one.

Besides, I think it's a better practice to define BLOCK_ADDR as either a UVM configuration variable (so that it can be modified at run time), or at least as a parameter. And, I think it's better to use start_item/finish_item instead of any of these `uvm_do_* macros, and do a randomize with after you start_item. In general, I'd avoid the preprocessor as much as possible, with a couple of exceptions (factory registration, UVM message reporting).

[raghavendrap]

thank you meal201.

I am able to pass the define in `uvm_do_with, seems its like a glitch in my env

fyi, i am re-using the `BLOCK_ADDR defined in RTL file