
enchanter
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When I play around with the factory/basic example from uvm-systemc-1.0-beta1, In the original example code, it prints the instance override information as below: UVM_INFO @ 0 s: reporter [RNTST] Running test ... UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] #### Print Factory Configuration (*) Instance Overrides: Requested Type Override Path Override Type -------------- ------------- ------------- gen top.e.gen1 mygen Type Overrides: Requested Type Override Type -------------- -------------
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I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2 I got error as below and I have no idea what I have done wrong. ~/systemc/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h:87:7: error: inherited virtual base class 'sc_core::sc_interface' has private destructor class tlm_master_imp : ^ I have attached the full compile log comp.log
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Build issues with UVM-SystemC 1.0-beta1
enchanter replied to hle's topic in SystemC Verification (UVM-SystemC, SCV)
For the build issue, I think you can over CMake configure in SystemC to set library path to wherever you want. -
UVM-SystemC 1.0-beta1 Released
enchanter replied to Lynn Garibaldi's topic in SystemC Verification (UVM-SystemC, SCV)
Any plan to fix this build error on Mac OS? libtool: link: ar cru .libs/libmacros.a ar: no archive members specified usage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...] make[4]: [libmacros.la] Error 1 (ignored) -
UVM-SystemC 1.0-beta1 Released
enchanter replied to Lynn Garibaldi's topic in SystemC Verification (UVM-SystemC, SCV)
In installed uvm-systemc.pc file, it sets Libs to "-luvm". Should it be "-luvm-systemc"? -
Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS. When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why.
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I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
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I am learning the TLM example at_4_phase in the SystemC 2.3.1 package. But I don't know why there are 16 WRITE commands are generated by the traffic_generator? From my understanding, the m_transaction_queue is enqueue-ed twice. So I think it should only generate 2 commands then the queue should be empty. Why it generate 16 WRITE and 16 READ commands instread?