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sending register sequences from virtual sequence


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Hi

in my env I have few masters agents and register adapter for each master agent.

each register sequence uses different regmodel from env

I would like to create virtual sequence to send register sequences on these masters.

I would like to use command line option ti get sequence name and run the test.

any suggestion how can I do this ?

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  • 2 months later...

Hi Verifier,

I don't have a full solution, but here is an idea. Create a base virtual sequence which can start a register sequence. For each agent + uvm_reg_map, create a subclass of the base virtual sequence which connects the register sequence to the specific agent. Use +uvm_set_inst_override or +uvm_set_type_override command line options to override the instantiation of the base virtual sequence in your environment to a specific subclass. It is late for me, so I'm not sharp enough to give you any code, but does this help you some of the way?

Best Regards

Peter

http://www.vmmcentral.org/uvm_vmm_ik/files3/base/uvm_cmdline_processor-svh.html

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