UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. Can uvm_reg_predictor auto-compare the read values if register read is performed ?

   By saraba83, February 27, 2013
   • 0 replies
   • 1.6k views
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   • saraba83
   • February 27, 2013

2. UVM phase method names and arguments - are they really necessary?

   By cliffc, February 23, 2013
   • 6 replies
   • 4.6k views
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   • dave_59
   • February 24, 2013

3. How can I run APB example contained in UVM1.1c tarball?

   By rogers, February 24, 2013
   • 1 reply
   • 1.2k views
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   • janick
   • February 24, 2013

4. use create() for constructor with additional arguments

   By wilsony, February 15, 2013
   • 6 replies
   • 21k views
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   • cliffc
   • February 23, 2013

5. Sequence Libraries / uvm_sequence_library

   By cliffc, February 23, 2013
   • 0 replies
   • 1.5k views
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   • cliffc
   • February 23, 2013

6. multiple threads of a sequence on different instances of same agents

   By alltech, February 22, 2013
   • 0 replies
   • 1.1k views
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   • alltech
   • February 22, 2013

7. Default phase sequence for phases in sequencer

   By smallnokia, February 13, 2013
   • 2 replies
   • 6.1k views
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   • smallnokia
   • February 15, 2013

8. global_stop_request() does not work in UVM?

   By cliffc, February 12, 2013
   • 3 replies
   • 7.2k views
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   • smallnokia
   • February 13, 2013

9. Virtual sequence & configuration db

   By carningli, February 1, 2013
   • 1 reply
   • 1.6k views
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   • jadec
   • February 12, 2013

10. -DUVM_MUTE option

    By bdasari, January 30, 2013
    • 1 reply
    • 1.1k views
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    • jadec
    • February 12, 2013

11. Usage of heartbeat in UVM to terminate simulation

    By Jignesh, February 5, 2013
    • 2 replies
    • 3k views
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    • sri.cvcblr
    • February 10, 2013

12. Unexpected behavior of uvm_tlm_fifo (Bug or bad usage?)

    By mpeer, February 8, 2013
    • 5 replies
    • 3k views
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    • sri.cvcblr
    • February 10, 2013

13. reuse driver on various interfaces, diff by data width only

    By wilsony, January 30, 2013
    • 7 replies
    • 1.9k views
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    • dave_59
    • January 30, 2013

14. UVM Register Package

    By neil, January 25, 2011
    • 5 replies
    • 4k views
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    • Discovery
    • January 22, 2013

15. Dropping objection from within a sequence

    By carningli, January 15, 2013
    • 6 replies
    • 8.4k views
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    • carningli
    • January 22, 2013

16. unique register model name issue

    By mwhite_cp, January 18, 2013
    • 0 replies
    • 1.3k views
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    • mwhite_cp
    • January 18, 2013

17. Sequence/test library file vs sequence/test files

    By mwhite_cp, January 11, 2013
    • 3 replies
    • 1.8k views
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    • petermonsson
    • January 18, 2013

18. Inter Sequence communication

    By kiranbhaskar, September 16, 2011
    • 10 replies
    • 7.8k views
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    • whiteriver
    • January 17, 2013

19. How to add a transparent sequence router?

    By Logger, January 10, 2013
    • 1 reply
    • 1.2k views
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    • petermonsson
    • January 14, 2013

20. Sequence item overriding is not working(set_type_override)

    By dave_345, December 24, 2012
    • 2 replies
    • 2.9k views
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    • uwes
    • January 14, 2013

21. uvm skipping phase problem

    By mrforever, December 31, 2012
    • 9 replies
    • 3.9k views
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    • uwes
    • January 14, 2013

22. why is `uvm_do not implemented as a task?

    By Logger, January 10, 2013
    • 2 replies
    • 1.3k views
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    • Logger
    • January 11, 2013

23. How to execute code in a component after a UVM_FATAL?

    By dwikle, January 10, 2013
    • 5 replies
    • 6.9k views
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    • dwikle
    • January 11, 2013

24. cryptography verification using UVM

    By saket, January 11, 2013
    • 0 replies
    • 958 views
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    • saket
    • January 11, 2013

25. one bug in uvm-1.1c library about uvm_reg

    By mrforever, January 8, 2013
    • 1 reply
    • 1.2k views
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    • mrforever
    • January 9, 2013