Roman Posted August 13, 2012 Report Share Posted August 13, 2012 In one case, DUT slave control sends complete response on bus but the data didn't arrive at the register internal DUT. the real data update to register need more time . but the bus2reg will update the register model at once. If we make backdoor read or backdoor mirror immediately after write(frontdoor) , the data will be old (the checking will fail). besides wait for some clock cycles or wait for some signals toggle after calling write() , How to make sure the real write complete after write() method returned in this case? the wait for some clock cycles will be unexpected. The way of polling something will eat the performance. Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.