UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. register access issue

   By sachint, March 30, 2012
   • 0 replies
   • 797 views
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   • sachint
   • March 30, 2012

2. Starting with UVM

   By domenico, March 29, 2012
   • 2 replies
   • 2.1k views
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   • dave_59
   • March 30, 2012

3. [ubus example] is there a redundant uvm_config_db::get in ubus_env? (num_masters)

   By SeanChou, March 23, 2012
   • 5 replies
   • 2.7k views
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   • Roman
   • March 30, 2012

4. Should user's base classes be registered with factory?

   By mastrick, March 22, 2012
   • 2 replies
   • 1.6k views
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   • Roman
   • March 28, 2012

5. uvm_mem backdoor access

   By mwhite_cp, March 27, 2012
   • 3 replies
   • 4.7k views
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   • mwhite_cp
   • March 27, 2012

6. uvm_objection_cbs_t :: Not working as recommended !!

   By nndad, March 20, 2012
   • 4 replies
   • 1.7k views
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   • nndad
   • March 22, 2012

7. type_id of the uvm_sequence_base

   By drianf0, March 16, 2012
   • 2 replies
   • 2k views
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   • drianf0
   • March 20, 2012

8. UVM vimrc file

   By paragsathe, March 20, 2012
   • 0 replies
   • 1.2k views
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   • paragsathe
   • March 20, 2012

9. Change radix value for transaction recording.

   By steveb, March 14, 2012
   • 3 replies
   • 1.5k views
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   • uwes
   • March 16, 2012

10. How to pass information between two agents?

    By enchanter, March 10, 2012
    • 4 replies
    • 2k views
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    • enchanter
    • March 14, 2012

11. UVM Express Step 2: Unit Testing Coverage Groups and UVM Agents

    By nosnhojn, March 12, 2012
    • 0 replies
    • 1.2k views
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    • nosnhojn
    • March 12, 2012

12. model memory using uvm_reg array

    By mwhite_cp, March 9, 2012
    • 0 replies
    • 1.3k views
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    • mwhite_cp
    • March 9, 2012

13. Test stop [TEST_DONE] before the sequencer drop_objection

    By enchanter, March 9, 2012
    • 1 reply
    • 2.5k views
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    • uwes
    • March 9, 2012

14. How to use phase_ready_to_end?

    By IChip, March 4, 2012
    • 7 replies
    • 11.4k views
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    • IChip
    • March 7, 2012

15. Hierachical configuration class

    By fbochud, February 22, 2012
    • 5 replies
    • 2k views
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    • fbochud
    • March 7, 2012

16. How to use new sequence item (extended from base sequence item & has new members)

    By anantv, March 6, 2012
    • 8 replies
    • 5.6k views
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    • anantv
    • March 7, 2012

17. Why do uvm_reg::read() and uvm_reg::mirror compare against m_desired?

    By jeff.schroeder, March 6, 2012
    • 0 replies
    • 2.2k views
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    • jeff.schroeder
    • March 6, 2012

18. Why I Like UVM Express

    By nosnhojn, February 27, 2012
    • 2 replies
    • 1.7k views
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    • nosnhojn
    • March 2, 2012

19. uvm_queue and do_compare

    By drianf0, March 2, 2012
    • 1 reply
    • 2.4k views
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    • uwes
    • March 2, 2012

20. virtual sequece or virtual sequencer

    By shail, March 1, 2012
    • 1 reply
    • 1.7k views
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    • Roman
    • March 2, 2012

21. cloning before write()

    By janick, February 27, 2012
    • 5 replies
    • 3.4k views
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    • janick
    • March 1, 2012

22. UVM Enhancement uvm_root::set_timeout() should use uvm_tlm_time rather then time

    By ryz, February 20, 2012
    • 4 replies
    • 4.2k views
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    • ryz
    • February 24, 2012

23. Configuration recommendations in the UVM

    By gbbrown, August 24, 2011
    • 10 replies
    • 7.5k views
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    • janick
    • February 22, 2012

24. Constaining register fields from the testcase

    By paragsathe, February 20, 2012
    • 3 replies
    • 2.9k views
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    • Roman
    • February 21, 2012

25. How to correctly kill an virtual sequence

    By ryz, February 20, 2012
    • 2 replies
    • 5.5k views
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    • ryz
    • February 20, 2012